MSM518222A-30JS Oki Semiconductor, MSM518222A-30JS Datasheet

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MSM518222A-30JS

Manufacturer Part Number
MSM518222A-30JS
Description
Manufacturer
Oki Semiconductor
Datasheet
E2L0067-18-Z2
This version: Dec. 1998
¡ Semiconductor
¡ Semiconductor
MSM518222A
MSM518222A
262,214-Word ¥ 8-Bit Field Memory
DESCRIPTION
The OKI MSM518222A is a high performance 2-Mbit, 256K ¥ 8-bit, Field Memory. It is designed
for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital
movies and Multi-media systems. It is a FRAM for wide or low end use as general commodity
TVs and VTRs, exclusively. The MSM518222A is not designed for the other use or high end use
in medical systems, professional graphics systems which require long term picture, and data
storage systems and others. The 2-Mbit capacity fits one field of a conventional NTSC TV screen.
Two cascaded MSM518222As make one frame of the screen: two or more MSM518222As can be
cascaded directly without any delay devices between them. (Cascading provides larger storage
depth or a longer delay).
Each of the 8-bit planes has separate serial write and read ports. These employ independent control
clocks to support asynchronous read and write operations. Different clock rates are also supported,
which allow alternate data rates between write and read data streams.
The MSM518222A provides high speed FIFO, First-In First-Out, operation without external refreshing:
it refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial
access operation, so that serial read and/or write control clock can be halted high or low for any
duration as long as the power is on. Internal conflicts of memory access and refreshing operations
are prevented by special arbitration logic.
The MSM518222A's function is simple, and similar to a digital delay device whose delay-bit-length
is easily set by reset timing. The delay length, and the number of read delay clocks between write
and read, is determined by externally controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256 ¥ 8-bit enable high speed
first-bit-access with no clock delay just after the write or read reset timings.
The MSM518222A is similar in operation and functionality to OKI 1-Mbit Field Memory
MSM514221B, with the addition of cascade capability. (As for MSM514221B operation compatible
2-Mbit Field Memory, OKI has the MSM518221A which is a sister device of MSM518222A).
Additionally, the MSM518222A has a write mask function or input enable function (IE), and read-
data skipping function or output enable function (OE). The differences between write enable (WE)
and input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE can
stop serial write/read address increments, but IE and OE cannot stop the increment, when write/
read clocking is continuously applied to MSM518222A. The input enable (IE) function allows the
user to write into selected locations of the memory only, leaving the rest of the memory contents
unchanged. This facilitates data processing to display a "picture in picture" on a TV screen.
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MSM518222A-30JS Summary of contents

Page 1

... HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media systems FRAM for wide or low end use as general commodity TVs and VTRs, exclusively. The MSM518222A is not designed for the other use or high end use in medical systems, professional graphics systems which require long term picture, and data storage systems and others ...

Page 2

... ZIP 28-pin 400 mil plastic SOJ 28-pin 430 mil plastic SOP PRODUCT FAMILY Family Access Time (Max.) MSM518222A-25ZS MSM518222A-30ZS MSM518222A-40ZS MSM518222A-25JS MSM518222A-30JS MSM518222A-40JS MSM518222A-30GS-K MSM518222A-40GS-K 25 ns/30 ns/ ns/25 ns/30 ns (ZIP28-P-400-1.27) (Product : MSM518222A-xxZS) (SOJ28-P-400-1.27) (Product : MSM518222A-xxJS) (SOP28-P-430-1.27-K) (Product : MSM518222A-xxGS-K) xx indicates speed rank ...

Page 3

... Read Enable IE Input Enable OE Output Enable RSTW Write Reset Clock RSTR Read Reset Clock Data Input Data Output OUT V Power Supply ( Ground ( Connection MSM518222A ...

Page 4

RE D (¥ OUT Data-out Serial Read Buffer (¥ 8) 512-Word Serial Read Register (¥ 8) Read Line Buffer Low-Half (¥ 8) 256 (¥ 8) 71-Word Sub-Register (¥ 8) 256K (¥ 8) Memory Array 71-Word Sub-Register (¥ 8) ...

Page 5

... DRAM array, an RSTW operation is required after the last SWCK cycle. Note that every write timing of MSM518222A is delayed by one clock compared with read timings for easy cascading without any interface delay devices. Write Reset : RSTW The first positive transition of SWCK after RSTW becomes high resets the write address counters to zero ...

Page 6

... The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same polarity as data in. The output becomes valid after the access time interval t begins with the rising edge of SRCK. *There are no output valid time restrictions on MSM518222A. Read Enable : RE The function gate the SRCK clock for incrementing the read pointer ...

Page 7

... It may be "old data" or "new" data combination of old and new data. Such a timing should be avoided. Cascade Operation The MSM518222A is designed to allow easy cascading of multiple memory devices. This provides higher storage depth longer delay than can be achieved with only one memory device. MSM518222A ...

Page 8

... Other Pins Tested < V < – -25 -30 Minimum Cycle Time, Output Open -40 Input Pin = MSM518222A Rating Unit –1 °C –55 to 150 °C Max. Unit 5 ...

Page 9

... WOEH OE "L" Pulse Width t WOEL RSTR Setup Time t RSTRS RSTR Hold Time t RSTRH t SWCK Cycle Time SWC SRCK Cycle Time t SRC Transition Time (Rise and Fall) MSM518222A-25 MSM518222A-30 MSM518222A-40 Min. Max. Min. — 25 — — — — ...

Page 10

... However, normal write is achieved in this address condition. 6. Outputs are measured with a load equivalent to 1 TTL load and 30 pF. Output reference levels are V is defined transition time that signal transfers ns 2.4 V and MSM518222A = 3.0 V and 10/16 ...

Page 11

... Write Cycle Timing (Write Enable) n cycle SWCK t WENH WE t WWEL n RSTW 0 cycle 1 cycle t t WSWH WSWL t RSTWH t SWC n 0 Disable cycle Disable cycle t t WDSH WDSS t WWEH n MSM518222A 2 cycle 1 2 n+1 cycle t WENS n+1 11/ ...

Page 12

... RSTRS t T RSTR OUT RE OE n+1 cycle n+2 cycle t t IDSH IDSS t WIEH n 0 cycle 1 cycle t t WSRH WSRL t RSTRH t SRC t DDCK 0 1 MSM518222A n+3 cycle t IENS n+3 2 cycle 2 12/ ...

Page 13

... Read Cycle Timing (Output Enable) n cycle SRCK t OENH OE t WOEN n OUT RE RSTR Disable cycle Disable cycle t t RDSH RDSS t WREH    n n+1 cycle n+2 cycle t t ODSH ODSS t WOEH Hi-Z MSM518222A n+1 cycle t RENS n+1 n+3 cycle t OENS t DECK n+3 13/ ...

Page 14

... Semiconductor PACKAGE DIMENSIONS ZIP28-P-400-1.27 Mirror finish MSM518222A (Unit : mm) Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating more Solder plate thickness Package weight (g) 1.85 TYP. 14/16 ...

Page 15

... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM518222A (Unit : mm) Package material Epoxy resin ...

Page 16

... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM518222A (Unit : mm) Package material Epoxy resin ...

Page 17

NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application ...

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