MSM54V16282-60TS-K Oki Semiconductor, MSM54V16282-60TS-K Datasheet
MSM54V16282-60TS-K
Related parts for MSM54V16282-60TS-K
MSM54V16282-60TS-K Summary of contents
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... MSM54V16282 262,144-Word ¥ 16-Bit Multiport DRAM DESCRIPTION The MSM54V16282 is a 4-Mbit CMOS multiport DRAM composed of a 262,144-word by 16-bit dynamic RAM, and a 512-word by 16-bit SAM. Its RAM and SAM operate independently and asynchronously. It supports three types of operations: random access to RAM port, high speed serial access to SAM port, and bidirectional transfer of data between any selected row in the RAM port and the SAM port ...
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... 70/64-Pin Plastic TSOP (II) (K Type) Pin Name SC SE DSF QSF pin. SS MSM54V16282 SDQ15 66 DQ15 65 SDQ14 64 DQ14 SDQ13 61 DQ13 60 SDQ12 59 DQ12 SDQ11 56 DQ11 ...
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Column Column Decoder Address Buffer Sense Amp. Row 512 ¥ 512 ¥ 16 Address RAM ARRAY Buffer Refresh Gate Counter SAM Serial Decoder SAM SAM Address Address Counter Buffer SAM Stop Control Block Write Column Mask Control ...
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... £ V £ All other pins not LI under test = £ V £ V OUT Output Disable MSM54V16282 (Note: 1) Rating Unit –0 °C –55 to 150 °C (Ta = 0°C to 70°C) (Note: 2) Max. Unit 3 0.3 ...
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... Active I RC CC5 Standby I CC6 Active I CC6 Standby I CC7 Active I CC7 Standby I CC8 Active I CC8 Standby I CC9 MSM54V16282 (V = 3.3 V ±0 0°C to 70°C) CC -60 -70 Unit Note Max. Max. 120 110 160 150 120 110 160 ...
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... RRH t 0 — 0 WCS t 10 — 10 WCH t 50 — 55 WCR t 10 — — 15 RWL t 15 — 15 CWL MSM54V16282 Unit Note Max. — ns — ns — ns — — ns 10k ...
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... THS t 10 — 10 THH t 0 — 0 TLS t 10 10k 10 TLH t 50 10k 60 RTH t 20 — 25 ATH t 15 — 20 CTH MSM54V16282 Unit Note Max. — — — ns — — — — ns — — ns — ns — ...
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... SDH t 0 — 0 SZE t 0 — 0 SZS t 0 — 0 SWS t 10 — 10 SWH t 0 — 0 SWIS t 10 — 10 SWIH MSM54V16282 Unit Note Max. — ns — ns — ns — ns — ns — ns — ns — — ns — ns — — ...
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... AWD (Max.) limit ensures that t RCD (Max.) limit ensures that t RAD RAD / SOH COH SCA MSM54V16282 and (Min.), t t RWD RWD CWD CWD (Max.) can be met. RAC is greater than the specified RCD ...
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... DQ0 - 7 Open DQ8 - THS THH TRG RAS t CSH t RSH t CAS t RAL t t ASC CAH Column FHR t t FSC CFH t RCS t CAC t AA Valid Data t RAC Valid Data t ROH t OEA MSM54V16282 RRH t RCH t OFF t OEZ "H" or "L" 10/39 ...
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... FSC CFH FSC CFH t RCS t t RCS RCH t t CAC CAC OFF Valid Data t RAC t CPA Valid Data t OEA MSM54V16282 t RSH CAS CP CAS t RAL t t CAH ASC CAH Column t t FSC CFH t t RCH RCS t RCH t CAC t AA ...
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... Column 0 ( Column 1 ( Column 2 ( Column 3 ( Column 4 ( Column 5 ( Column 6 ( Column 7 ( MSM54V16282 Function Low : Mask High : No Mask Low : Mask High : No Mask 12/39 ...
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... MS MH DQ8 - THS THH TRG RAS t CSH t RSH t CAS t RAL t t ASC CAH Column t FHR t t FSC CFH B t CWL t RWL WCS WCH t DHR DHR MSM54V16282 t RP "H" or "L" 13/39 ...
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... DQ8 - THS TRG RAS t CSH t RSH t CAS t RAL t t ASC CAH Column t FHR t t FSC CFH B t CWL t t RCS RWL WCR t RCS t DHR DHR OEH MSM54V16282 t RP "H" or "L" 14/39 ...
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... CAS t RAL t t ASC CAH Column t AWD t t FSC CFH B t CWL RCS CWD RWL RWD t RCS t CAC t RAC t t DZC DS DH Valid E Data Valid E Data DZO OEZ OEA OEH MSM54V16282 t RP "H" or "L" 15/39 ...
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... FSC CFH CWL CWL WCS WCH WCH MSM54V16282 RSH CAS t RAL t t ASC CAH Column t t FSC CFH B t CWL WCS WCH ...
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... CWD CWD t t CAC CAC Out In Out In Out In Out OEZ OEZ t t OEA OEA MSM54V16282 RSH CAS t RAL t t ASC CAH Column t t FSC CFH B t CWL t AWD CWD t CAC ...
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... Semiconductor RAS Only Refresh Cycle RAS t CRP CAS t t ASR RAH Address Row t t FSR RFH DSF WEL/U DQ0 - THS THH TRG RAS Open MSM54V16282 RPC "H" or "L" 18/39 ...
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... Semiconductor CAS before RAS Refresh Cycle t RP RAS t t RPC CSR CAS Address DSF WEL/U t OFF DQ0 - 15 TRG RAS t CHR Inhibit Falling Transition Open MSM54V16282 RPC "H" or "L" 19/39 ...
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... Semiconductor CAS before RAS Self-Refresh Cycle t RP RAS t t RPC CSR CAS t OFF DQ0 - 15 Address, DSF, WEL, WEU, TRG = "H" or "L" Note RASS RPS t RPC t CHS Open MSM54V16282 "H" or "L" 20/39 ...
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... WEL/U Open DQ0 - THS THH TRG RAS RSH t RAL t t ASC CAH Column t FHR t t FSC CFH t RCS t RRH t CAC RAC t OEA MSM54V16282 t RAS t CHR t OFF Valid Data t OEZ "H" or "L" 21/39 ...
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... CSH t RSH t CAS AR t RAL t t ASC CAH SAM Start t ASD t CSD Open t RSD TSD t SCP Note CQD Note 3 MSM54V16282 TRP t SCC SCA t t SZS SCA SOH Data Out TQD Note 3 "H" or "L" 22/39 ...
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... QSF = "H"-- Upper SAM (256 - 511) is active RAS t CSH t RSH t CAS AR t RAL t t ASC CAH SAM Start t CTH t ATH Open RTH t t TSL TSD Data Out Data Out t TQD Note 2 MSM54V16282 TRP t SCA t SOH Data Out Note 2 "H" or "L" 23/39 ...
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... RSH t CAS AR t RAL t t ASC CAH SAM Start Sj t CTH t ATH Open t RTH t SCC t t SCP STOP t SCA t SOH Data Out Data Out Note 2 MSM54V16282 t RP STOP Data Out Data Out t SQD Note 2 "H" or "L" 24/39 ...
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... QSF = "H"-- Upper SAM (256 - 511) is active RAS t CSH t RSH t CAS AR t RAL t t ASC CAH SAM Start t CSD Open t RSD t SCP Note SDD t CQD Note 3 MSM54V16282 SCC SDS SDH SDS SDH Data In Data In Note 3 "H" or "L" 25/39 ...
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... CSH t RSH t CAS AR t RAL t t ASC CAH SAM Start Sj t CTH t ATH Open t RTH t SCC t t SCP STOP SDS SDH SDH Data In Data In Note 2 MSM54V16282 t RP STOP Data In Data In t SQD Note 2 "H" or "L" 26/39 ...
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... SCP SC t SDS SDQ0 - 15 Data In Data In t SEP t SCC SCP t t SEA Data t SEP SWH SWIS SWIH t SDH MSM54V16282 t t SCA SCA t SOH SOH Data Out Data Out t SWS t SDS t t SZE SDH Data In Data In "H" or "L" 27/39 ...
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... PIN FUNCTIONS Address Input The 18 address bits decode 16 bits of the 4,194,304 locations in the MSM54V16282 memory array. The address bits are multiplexed to 9 address input pins (A0 - A8) as standard DRAM. 9 row address bits are latched at the falling edge of RAS. The following 9 column address bits are latched at the falling edge of CAS ...
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... Serial Input/Output: SDQ0 - SDQ15 Serial input/output mode is determined by the most recent read or write transfer cycle. When a read transfer cycle is performed, the SAM port is in the output mode. When a write or pseudo write transfer cycle is performed, the SAM port is switched from output mode to input mode. MSM54V16282 29/39 ...
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... OPERATION MODES Table-1 shows the function truth table for a listing of all available RAM ports, and transfer operations of the MSM54V16282. The RAM port and data transfer operations are determined by the state of CAS, TRG, WEL, WEU and DSF at the falling edge of RAS, and by the level of DSF at the falling edge of CAS. ...
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... RAS. When the mask data is low, writing is inhibited into the RAM and the mask data is high, data is written into the RAM. This mask data is in effect during the RAS cycle. In page mode cycle the mask data is retained during page access. MSM54V16282 31/39 ...
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... Semiconductor Load/Read Color Register: RAS falling edge --- CAS = TRG = WEL = WEU = DSF = "H" The MSM54V16282 is provided with an on-chip 16-bit color register for use during the flash write or block write operation. Each bit of the color register corresponds to one of the DRAM I/O blocks ...
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... Note : Location "*" can not be loaded. Example of Block Write MSM54V16282 Bit 15 01110011 01101011 00111100 Upper Byte * * * * * * * * * * * * ...
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... SAM pointer moves to the TAP location selected for the second split SAM to shift data in or out sequentially, starts from this TAP location at the most significant bit (511 or 255), and finally wraps around to the least significant bit. TAP TAP 255 256 257 MSM54V16282 511 34/39 ...
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... The conventional transfer and split transfer modes are controlled by the DSF input signal. Data transfer is invoked by holding the TRG signal "low" at the falling edge of RAS. The MSM54V16282 supports 4 types of transfer operations: Read transfer, Split read transfer, Write transfer and Split write transfer as shown in the truth table. The type of transfer operation is determined by the state of CAS, WEL, WEU and DSF latched at the falling edge of RAS ...
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... AX8). WEL or WEU = "L" during the RAS cycle. A rising edge of the from the falling edge of the CAS, at which time CSD MSM54V16282 from the rising SCA or V after the and t ...
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... Semiconductor Split Data Transfer and QSF The MSM54V16282 features a bidirectional split data transfer capability between the RAM and SAM. During split data transfer operation, the serial register is split into two halves which can be controlled independently. Split read or split write transfer operation can be performed to or from one half of the serial register, while serial data can be shifted into or out of the other half of the serial register ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM54V16282 (Unit : mm) Package material Epoxy resin ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM54V16282 (Unit : mm) Package material Epoxy resin ...