YMF754-R Yamaha, YMF754-R Datasheet
YMF754-R
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YMF754-R Summary of contents
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... Hardware Volume Control • EEPROM Interface • Single Crystal operation (24.576MHz) • Power supply: 3.3V for I/O (5V tolerant), 2.5V for Internal core logic • 128-pin LQFP YMF754-V : 0.5mm pin pitch YMF754-R : 0.4mm pin pitch CATALOG No.:LSI-4MF754A00 Preliminary YMF754 CATALOG December 18, 1998 June 28, 1999 ...
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... YMF754 LOGOS GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry (AMEI), and indicates GM system level 1 Compliant. XG logo is a trademark of YAMAHA Corporation. SONDIUS-XG logo is a trademark that Stanford University in the United States and YAMAHA Corporation hold jointly. Sensaura logo is a trademark of Central Research Laboratories Limited. ...
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... YMF754 PIN CONFIGURATION YMF754-V (0.5mm pin pitch) AD26 1 PVDD2 2 AD25 3 AD24 4 CBE3# 5 IDSEL 6 AD23 7 PVSS4 8 AD22 9 AD21 10 AD20 11 AD19 12 AD18 13 AD17 14 AD16 15 CBE2# 16 PVSS3 17 FRAME# 18 IRDY# 19 TRDY# 20 DEVSEL# 21 PVDD1 22 STOP# 23 PERR# 24 SERR# 25 PAR 26 CBE1# 27 PVSS2 28 AD15 29 AD14 30 AD13 31 AD12 32 AD11 33 AD10 ...
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... YMF754 YMF754-R (0.4mm pin pitch) AD24 1 CBE3# 2 IDSEL 3 4 AD23 5 PVSS4 AD22 6 AD21 7 AD20 8 AD19 9 10 AD18 11 AD17 AD16 12 CBE2# 13 PVSS3 14 FRAME# 15 IRDY# 16 TRDY# 17 DEVSEL# 18 PVDD1 19 STOP# 20 PERR SERR# PAR 23 CBE1# 24 PVSS2 25 AD15 26 AD14 27 28 AD13 AD12 29 AD11 30 AD10 31 AD9 ...
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... YMF754 PIN DESCRIPTION 1. PCI Bus Interface (54-pin) Name I/O PCICLK I RST# I AD[31:0] IO C/BE[3:0]# IO PAR IO FRAME# IO IRDY# IO TRDY# IO STOP# IO IDSEL I DEVSEL# IO REQ# O GNT# I PCREQ# O PCGNT# I PERR# IO SERR# O INTA# O SERIRQ# IO CLKRUN AC’97 Interface (8-pin) Name I/O CRST# O CMCLK O CBCLK I CSDO O CSYNC O CSDI0 I CSDI1 I DOCKEN# I Type ...
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... YMF754 3. External Audio Interface (5-pin) Name I/O SPDIFOUT O SPDIFIN I ZVBCLK I ZVLRCK I ZVSDI I 4. Legacy Device Interface (15-pin) Name I/O IRQ5 O IRQ7 O IRQ9 O IRQ10 O IRQ11 O GP[3:0] I GP[7:4] I RXD I TXD O 5. Miscellaneous (11-pin) Name I/O ROMCS O ROMSK / VOLUP# IO ROMDO / VOLDW# IO ROMDI I XI24 I XO24 O LOOPF I GPIO[2:0] IO TEST# I Type ...
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... YMF754 6. Power Supply (22-pin) Name I/O PVDD[3:0] - PVSS[6:0] - CVDD[2:0] - VDD[2:0] - VSS[2:0] - LVDD - LVSS - 7. Reserve Pin (13-pin) Name I/O RESERV[12:0] - TYPE T : TTL Ttr : Tri-State TTL Tup : Pull up (Max. 300kohm) TTL Type Size - - 3.3V Power supply for PCI Bus Interface - - Ground for PCI Bus Interface - - 2.5V Power supply for Core logic ...
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... YMF754 BLOCK DIAGRAM EEPROM I/F GPIO Clock Run PCI Side Band Legacy Audio PC/PCI S-IRQ PCI Interface Audio Function Config PCI Audio Register ZV Port SPDIF Input FM Synthesizer SB Pro D-DMA Engine MPU401 Joystick PCI Bus Master DMA Controller XG Synthesizer DirectSound Acc. Wave In/Out ...
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... YMF754 FUNCTION OVERVIEW 1. PCI INTERFACE DS-1E supports the PCI bus interface and complies to PCI revision 2.2. 1-1. PCI Bus Command DS-1E supports the following PCI Bus commands. 1-1-1. Target Device Mode C/BE[3:0 ...
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... YMF754 1-2. PCI Configuration Register In addition to the Configuration Register defined by PCI Revision 2.2, DS-1E provides proprietary PCI Configuration Registers in order to control legacy audio function, such as FM Synthesizer, Sound Blaster Pro, MPU401 and Joystick. These additional registers are configured by BIOS or the configuration software from YAMAHA Corporation. ...
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... YMF754 00-01h: Vendor ID Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b[15:0] ........Vendor ID This register contains the YAMAHA Vendor ID registered in Revision 2.2. This register is hardwired to 1073h. 02-03h: Device ID Read Only Default: 0012h Access Bus Width: 8, 16, 32-bit b15 ...
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... YMF754 b6................PER: Parity Error Response This bit enables DS-1E responses to Parity Error. “0”: DS-1E ignores all parity errors. “1”: DS-1E performs error operation when DS-1E detects a parity error. b8................SER: SERR# Enable This bit enables DS-1E to drive SERR#. “0”: Do not drive SERR#. “1”: Drives SERR# when DS-1E detects an Address Parity Error on normal target cycle or a Data Parity Error on special cycle ...
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... YMF754 08h: Revision ID Read Only Default: 00h Access Bus Width: 8, 16, 32-bit Revision ID b[7:0] ..........Revision ID This register contains the revision number of DS-1E. This register is hardwired to 00h. 09h: Programming Interface Read Only Default: 00h Access Bus Width: 8, 16, 32-bit Programming Interface b[7:0] ...
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... YMF754 0Dh: Latency Timer Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit Latency Timer b[7:0] ..........Latency Timer When DS-1E becomes a Bus Master device, this register indicates the initial value of the Master Latency Timer. 0Eh: Header Type Read Only Default: 00h ...
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... YMF754 14-17h: Legacy Audio I/O Base Address (Dummy for SB, FM, MPU, D-DMA) Read / Write Default: 00000001h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b31 b30 b29 b28 - - - - b0................IO (Read Only) This bit indicates that the base address is assigned to I/O. This bit is hardwired to “1”. ...
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... YMF754 2C-2Dh: Subsystem Vendor ID Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b[15:0] ........Subsystem Vendor ID This register contains the Subsystem Vendor ID. In general, this ID is used to distinguish adapters or systems made by different IHVs using the same chip by the same vendor. This register is read only. To write the IHV’ ...
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... YMF754 3Ch: Interrupt Line Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit Interrupt Line b[7:0] ..........Interrupt Line This register indicates the interrupt channel that INTA# is assigned to. 3Dh: Interrupt Pin Read Only Default: 01h Access Bus Width: 8, 16, 32-bit b7 b6 ...
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... YMF754 40-41h: Legacy Audio Control Read / Write Default: 907Fh Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 LAD SIEN MPUIRQ b0................SBEN: Sound Blaster Enable This bit enables the mapping of the Sound Blaster Pro block in the I/O space specified by 62-63h: Sound Blaster Base Address register, when LAD is set to “0”. ...
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... YMF754 b[7:6] ..........SDMA: Sound Blaster DMA-8 Channel Select These bits select the DMA channel for the Sound Blaster Pro block. “0”: DMA ch0 “1”: DMA ch1 “2”: reserved “3”: DMA ch3 b[10:8] ........SBIRQ: Sound Blaster IRQ Channel Select These bits select the interrupt channel for the Sound Blaster Pro block. ...
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... YMF754 b15..............LAD: Legacy Audio Disable This bit disables the Legacy Audio block. “0”: Enables the Legacy Audio block “1”: Disables the Legacy Audio block When this bit is set to “1”, DS-1E does not respond to the I/O Target transaction for legacy I/O address on the PCI bus ...
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... YMF754 44-45h: Subsystem Vendor ID Write Read / Write Default: 1073h Access Bus Width: 16-bit b15 b14 b13 b12 b[15:0] ........Subsystem Vendor ID Write This register sets the Subsystem Vendor ID that is read from 2C-2Dh (Subsystem Vendor ID register). The default value is the YAMAHA Vendor ID, 1073h. IHVs must change this ID to their Vendor ID in the BIOS POST routine ...
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... YMF754 b2................WRST: AC’97 Warm Reset This bit places the AC’97 in warm reset condition when the BIT_CLK signal on the AC’97 remains in inactive state. If this bit is set to “1”, it will automatically return to “0” after 1.3µs time duration. This bit is valid only while the ACLS bit is set to “0”. Except in this case, even if this bit is attempted to be set to “ ...
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... YMF754 b9................PR1: AC’97 Power Down Control 1 This bit controls the power state of the DAC in the Primary AC’97. “0”: Normal (default) “1”: Power down b10..............PR2: AC’97 Power Down Control 2 This bit controls the power state of the Analog Mixer (Vref still on) in the Primary AC’97. This power state retains the Reference Voltage of the AC’ ...
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... YMF754 4C-4Dh: D-DMA Slave Configuration Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b0................CE: Channel Enable This bit enables the Distributed DMA function. “0”: Disable Distributed DMA “1”: Enable Distributed DMA b[2:1] ..........TS: Transfer Size These bits indicate the size of the DMA transfer. Since DS-1E supports only 8-bit DMA transfer, the bits are hardwired to 00b ...
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... YMF754 b3................PSMPU: Power Save MPU401 Setting this bit to “1” stops a clock supplied to the MPU401 block. “0”: Normal (default) “1”: Disable b4................PSJOY: Power Save Joystick Setting this bit to “1” disables the comparator of the Joystick block. “0”: Normal (default) “ ...
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... YMF754 b11..............PSIO: Power Save I/O Pad Setting this bit to “1” cuts the pull up resistor of the input pins except for the PCI interface and AC-Link. The input signals keep the level before PSIO bit is set from “0” to “1”. In case the input level is only “ ...
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... YMF754 50h: Capability ID Read Only Default: 01h Access Bus Width: 8, 16, 32-bit Capability ID b[7:0] ..........Capability ID: Capability Identifier This register indicates that the new capability register is for Power Management control. This register is hardwired to 01h. 51h: Next Item Pointer Read Only Default: 00h ...
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... YMF754 54-55h: Power Management Control / Status Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 - - - - b[1:0] ..........PS: Power State These bits determine the power state of DS-1E. DS-1E supports the following power states: “0”: D0 “1”: D1 (not supported) “2”: D2 “3”: ...
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... YMF754 b1................SPR1: Secondary AC’97 Power Down Control 1 This bit controls the power state of the DAC in the Secondary AC’97. “0”: Normal (default) “1”: Power down b2................SPR2: Secondary AC’97 Power Down Control 2 This bit controls the power state of the Analog Mixer (Vref still on) in the Secondary AC’97. This power state retains the Reference Voltage of the AC’ ...
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... YMF754 60-61h: FM Synthesizer Base Address Read / Write Default: 0388h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b[15:2] ........FM Synthesizer Base Address This register sets the base address of the FM synthesizer. If b5:I/O bit of 40h register is set to “1”, b[9:2] bits are decoded by ignoring b[15:10] bits. 62-63h: Sound Blaster Base Address ...
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... YMF754 2. ISA Compatible Device DS-1E contains the following functions to maintain the compatibility with the past ISA Sound Devices. These devices are considered Legacy devices and the functions are referred to as Legacy Audio. Legacy Audio is independent from PCI Audio and can be used simultaneously. ...
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... YMF754 DS-1E supports PC/PCI and D-DMA protocols to emulate the DMA of SB Pro on the PCI. In addition, DS- 1E supports the old type of interrupts used by ISA and the Serialized IRQ protocol. The combination of PC/PCI and Serialized IRQ is recommended for DS-1E. The system block diagram when using Intel chip set is shown below. ...
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... YMF754 2-1. FM Synthesizer Block FM Synthesizer Block is register compatible with YMF289B. However, Power Management register has been deleted because it is now controlled by the PCI Configuration Register. The following shows the FMBase I/O map of FM Synthesizer. FMBase (R) FMBase (W) FMBase+1 (R/W) FMBase+2 (W) FMBase+3 (R/W) The following shows the FM Synthesizer Block registers. ...
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... YMF754 2-1-2. FM Synthesizer Data Register FM Synthesizer Data Register Array 0 (R/W): Address D7 D6 00-01h 02h 03h 04h RST MT1 08h - NTS (*1) 20-35h AM VIB (*2) 40-55h KSL (*3) 60-75h (*4) 80-95h A0-A8h B0-B8h - - BDh DAM DVB C0-C8h (*6) (*6) (*5) E0-F5h - - FM Synthesizer Data Register Array 1 (R/W) Address D7 D6 00-01h 04h - - 05h ...
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... YMF754 2-2. Sound Blaster Pro Block Sound Blaster Pro block emulates the DSP commands of Sound Blaster and Sound Blaster Pro. Only playback functions are supported (record functions are not supported). compatibility for games designed so that every DSP command receives a correct response. ...
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... YMF754 2-2-1. DSP Command The following shows the list of DSP Commands that are supported by the SB Pro engine. Both SB and SB Pro commands are supported. CMD Support Function 10h o 8bit direct mode single byte digitized sound output 14h o 8bit single-cycle DMA mode digitized sound output ...
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... YMF754 2-2-2. Sound Blaster Pro Mixer The following shows the register map of the Mixer section of Sound Blaster Pro. Address b7 b6 00h 04h Voice Volume L 0Ah - - 0Ch - - 0Eh - - 22h Master Volume L 26h MIDI Volume L 28h CD Volume L* 2Eh Line Volume L* F0h SBPDA - F1h F2h ...
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... YMF754 (1) Volume for MIDI 0 mute 0 0000h mute 1 0000h mute 2 0000h mute 3 0000h mute 4 0000h mute 5 0000h mute 6 0000h mute 7 0000h The default is Master = 4, MIDI = 4 (-12dB). (2) Volume for Voice 0 mute 0 0000h mute 1 0000h mute 2 0000h mute 3 0000h mute 4 0000h mute 5 0000h mute ...
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... YMF754 2-2-3. SB Suspend / Resume The SB block can read the internal state as to support Suspend and Resume functions. The internal state is made up of 268 flip flops. To read the state, these states are shifted in order and read 8 bits at a time from the SCAN DATA register. ...
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... YMF754 F1h: Scan In/ Out Data Read / Write Default: 00h SCAN DATA b[7:0] ..........SCAN DATA This is the data port for reading and writing the internal state. F2h: Current FM Synthesizer Index Read Only Default: 00h Current FM Synthesizer Index b[7:0] ..........Current FM Synthesizer Index This register indicates current index of the FM Synthesizer ...
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... YMF754 b7................FFEMP: FM Synthesizer Empty This bit indicates whether or not FIFO followed by the FM Synthesizer is empty. “0”: not Empty “1”: Empty (default) i) Scan Out SBPDA=0 SBPDR=1 SBPDA=1 SM=1 SS=1 SE=1 -> 0 Scan Data (Read) Suspend Preparation byte (Total Scan Data = 268 bit (33 byte bit)) ...
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... YMF754 2-2-4. SB IRQ Status F8h: Interrupt Flag Register Read Only Default: 00h b0................SBI: SB Interrupt Flag This bit indicates that the SB DSP occurs the interrupt. This bit is read only. Thus, read the SB DSP read port to clearing the interrupt and this bit. Then, the value of the read port is invalid. ...
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... YMF754 2-4. Joystick Joystick Block is the port for connecting IBM compatible analog joystick. The following shows the JSBase I/O map for Joystick. JSBase (R/W) Port D7 D6 +0h JBB2 JBB1 JACX... Joystick A, Coordinate X JACY... Joystick A, Coordinate Y JBCX... Joystick B, Coordinate X JBCY... Joystick B, Coordinate Y JAB1... Joystick A, Button 1 JAB2... ...
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... YMF754 3. DMA Emulation Protocol The former synthesizer LSI for the ISA bus such as the Sound Blaster used the DMA controller (8237: ISA DMAC) on the system to transfer the sound data from/to the host. For DS-1E, however, ISA DMAC must be used to transfer the sound data to the Sound Blaster Pro Block of the Legacy Audio Block ...
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... YMF754 3-2. D-DMA DS-1E provides the following registers to support D-DMA. D-DMA Slave Configuration Register (4C- 4Dh) of the PCI Configuration register is used to set the Base address of the Slave Address. Slave Address Base + 0h Base + 0h Base + 1h Base + 1h Base + 2h Base + 2h Base + 3h Base + 3h Base + 4h Base + 4h Base + 5h Base + 5h Base + 6h Base + 6h ...
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... YMF754 4. Interrupt Routing DS-1E supports three types of interrupts, interrupt signal on the PCI bus (INTA#), interrupt signal on the ISA bus (IRQ[5,7,9,10,11]), and Serialized IRQ. The IRQs on DS-1E are routed as shown below. INTA INTA# IRQ5 IRQ7 ISA IRQ IRQ9 IRQ10 IRQ11 SERIRQ# SERIRQ PCI Audio can only use INTA#, but the Sound Blaster Pro and MPU401 blocks of the Legacy Audio Block can use any of the three protocols ...
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... YMF754 5. Hardware Volume Control The hardware volume control determines the AC’97 master volume without using any software control using the external circuit listed below. Two pins, VOLUP# for increasing the volume and VOLDW# for decreasing the volume, are used. DS-1E provides a shadow register for the AC’97 master volume. When the software accesses the AC’97 master volume always reflected in the shadow register ...
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... YMF754 6. Digital Audio Interface DS-1E supports each system of the SPDIF input/output port compliant with the IEC958 specification. 6-1. SPDIF IN SPDIF input sampling frequency is 32.0kHz, 44.1kHz or 48.0kHz. In DS-1E, sampling rate of the SPDIF signal incoming from the SPDIFIN pin is converted to 48.0kHz in the frequency rate conversion stage in order to process all the signals at 48.0kHz frequency. If input sampling frequency is 48 ...
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... YMF754 7. Zoomed Video Port Zoomed Video Port is defined in the PC Card Standard (PCMCIA) applicable to the notebook PC or other systems. This port is used to directly output video and/or audio signals onto the PCMCIA bus for D/A conversion process, and connect them directly to the video and/or audio signal processing chips on the PC system ...
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... YMF754 8. Multiple AC’97 & Multi-Channel DS-1E allows connection with up to two AC’97s, and plays back up to 4-channel PCM data. Therefore, the following applications can be realized. 8-1. AC’97 Digital Docking AC’97 digital docking can be realized by mounting the secondary AC’97 on the docking station side. Typical example of digital docking connection between DS-1E and AC’ ...
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... YMF754 ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Item Power Supply Voltage (PVDD, VDD) Power Supply Voltage (CVDD, LVDD) Input Voltage Operating Ambient Temperature Storage Temperature Note : PVSS=VSS=LVSS=0[V] 2. Recommended Operating Conditions Item Power Supply Voltage (PVDD, VDD) Power Supply Voltage (CVDD, LVDD) Operating Ambient Temperature ...
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... YMF754 3. DC Characteristics Item High Level Input Voltage 1 High Level Input Voltage 1 Low Level Input Voltage 1 High Level Input Voltage 2 Low Level Input Voltage 2 High Level Input Voltage 3 Low Level Input Voltage 3 High Level Input Voltage 4 Low Level Input Voltage 4 Input Leakage Current ...
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... YMF754 4. AC Characteristics 4-1. Master Clock (Fig.1) Item XI24 Cycle Time XI24 High Time XI24 Low Time Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=2.5±0.2 V, LVDD=2.5±0.2 V XI24 4-2. Reset (Fig.2) Item Reset Active Time after Power Stable Power Stable to Reset Rising Edge Reset Slew Rate Note : Top = 0-70° ...
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... YMF754 4-3. PCI Interface (Fig.3, 4) Item PCICLK Cycle Time PCICLK High Time PCICLK Low Time PCICLK Slew Rate PCICLK to Signal Valid Delay Float to Active Delay Active to Float Delay Input Setup Time to PCICLK Input Hold Time for PCICLK Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=2.5±0.2 V, LVDD=2.5±0 *11: This characteristic is applicable to REQ# and PCREQ# signal ...
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... YMF754 4-4. AC’97 Master Clock Item CMCLK Cycle Time CMCLK High Time CMCLK Low Time CMCLK Rising Time CMCLK Falling Time Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=2.5±0.2 V, LVDD=2.5±0 CMCLK (Fig.5) Symbol Min. Typ 40.69 CMCYC CMHIGH t 8 CMLOW ...
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... YMF754 4-5. AC-link (Fig.6) Item CBCLK Cycle Time CBCLK High Time CBCLK Low Time CSYNC Cycle Time CSYNC High Time CSYNC Low Time CBCLK to Signal Valid Delay Output Hold Time for CBCLK Input Setup Time to CBCLK Input Hold Time for CBCLK Warm Reset Width Note) Top = 0-70° ...
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... YMF754 4-6. Zoomed Video Port Item ZVLRCK Delay Time ZVLRCK Setup Time ZVBCLK Low Time ZVBCLK High Time ZVSDI Setup Time ZVSDI Hold Time Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=2.5±0.2 V, LVDD=2.5±0 ZVLRCK ZVSCLK ZVSDI (Fig.7) Symbol Min. ...
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... YMF754 EXTERNAL DIMENSIONS YMF754-V 102 103 128 1 P-0.50Typ. The shape of the molded corner may slightly different from the shape in this diagram. The figure in the parenthesis ( ) should be used as a reference. Plastic body dimensions do not include burr of resin. UNIT : mm Note : The LSIs for surface mount need especial consideration on storage and soldering conditions. ...
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... YMF754 YMF754-R LEAD THICKNESS : 0.125Typ. or 0.15Typ. The shape of the molded corner may slightly different from the shape in this diagram. The figure in the parenthesis ( ) should be used as a reference. Plastic body dimensions do not include burr of resin. UNIT : mm Note : The LSIs for surface mount need especial consideration on storage and soldering conditions. ...
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... YMF754 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document ...