MSM5416283-50GS-K Oki Semiconductor, MSM5416283-50GS-K Datasheet
MSM5416283-50GS-K
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MSM5416283-50GS-K Summary of contents
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... MSM5416283 262,144-Word ¥ 16-Bit Multiport DRAM DESCRIPTION The MSM5416283 is a 4-Mbit CMOS multiport DRAM composed of a 262,144-word by 16-bit dynamic RAM, and a 512-word by 16-bit SAM. Its RAM and SAM operate independently and asynchronously. It supports three types of operations: random access to RAM port, high speed serial access to SAM port, and bidirectional transfer of data between any selected row in the RAM port and the SAM port ...
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... Plastic SSOP Pin Name SC SE DSF QSF pin. SS MSM5416283 SDQ15 61 DQ15 60 SDQ14 59 DQ14 SDQ13 56 DQ13 55 SDQ12 54 DQ12 SDQ11 51 DQ11 50 SDQ10 ...
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Column Column Decoder Address Buffer Sense Amp. Row 512 ¥ 512 ¥ 16 Address RAM ARRAY Buffer Refresh Gate Counter SAM Serial Decoder SAM SAM Address Address Counter Buffer SAM Stop Control Block Write Column Mask Control ...
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... £ V £ All other pins not LI under test = £ V £ 5.5 V OUT I LO Output Disable MSM5416283 (Note: 1) Rating Unit –1 °C –55 to 150 °C (Ta = 0°C to 70°C) (Note: 2) Max. Unit 5 ...
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... CC5 min.) Active I RC CC5 Standby I CC6 Active I CC6 Standby I CC7 Active I CC7 Standby I CC8 Active I CC8 MSM5416283 ( ±10 0°C to 70°C) CC -50 -60 -70 Unit Note Max. Max. Max. 140 130 120 180 170 160 ...
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... WCH t 40 — 50 — WCR t 8 — 10 — — 15 — RWL t 12 — 15 — CWL MSM5416283 -70 Unit Note Max. — ns — — — ns — — — — ...
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... THH t 0 — 0 — TLS t 8 10k 10 10k TLH t 40 10k 50 10k RTH t 20 — 20 — ATH t 15 — 15 — CTH MSM5416283 -70 Unit Note Max. 0 — — — — — — — — ...
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... SZE t 0 — 0 — SZS t 0 — 0 — SWS t 8 — 10 — SWH t 0 — 0 — SWIS t 8 — 10 — SWIH MSM5416283 -70 Unit Note Max. 50 — — — — — — — — ...
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... AWD (Max.) limit ensures that t RCD (Max.) limit ensures that t RAD RAD / SOH COH SCA MSM5416283 and (Min.), t t RWD RWD CWD CWD (Max.) can be met. RAC is greater than the specified RCD ...
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... RAS t CSH t RSH t RCD t CAS RAD RAL t t RAH ASC CAH Column t FHR t t FSC CFH t RCS t CAC t AA Open t RAC Open t ROH t OEA MSM5416283 CRL t RCH t RRH t OFF Valid Data Valid Data t OEZ "H" or "L" 10/40 ...
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... Open DQ8 - THS THH TRG RAS t CSH t RSH t CAS t RAL t t ASC CAH Column FHR t t FSC CFH t RCS t CAC t AA Valid Data t RAC Valid Data t ROH t OEA MSM5416283 RCL t RRH t RCH t OFF t OEZ "H" or "L" 11/40 ...
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... FSC CFH FSC CFH t RCS t t RCS RCH t t CAC CAC t t COH AA Valid Data RAC CPA Valid Data t OEA MSM5416283 t RSH CAS CP CAS t RAL t t ASC CAH Column t t FSC CFH t RCS t t RRH RCH t RCH t CAC ...
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... Column 0 ( Column 1 ( Column 2 ( Column 3 ( Column 4 ( Column 5 ( Column 6 ( Column 7 ( MSM5416283 Function DQ0 - 7 DQ8 - 15 Mask Mask Mask Mask Mask Mask — ...
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... MS MH DQ8 - THS THH TRG RAS t CSH t RSH t CAS t RAL t t ASC CAH Column t FHR t t FSC CFH B t CWL t RWL WCS WCH t DHR DHR MSM5416283 t RP "H" or "L" 14/40 ...
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... DQ8 - THS TRG RAS t CSH t RSH t CAS t RAL t t ASC CAH Column t FHR t t FSC CFH B t CWL t t RCS RWL WCR t RCS t DHR DHR OEH MSM5416283 t RP "H" or "L" 15/40 ...
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... CAS t RAL t t ASC CAH Column t AWD t t FSC CFH B t CWL RCS CWD RWL RWD t RCS t CAC t RAC t t DZC DS DH Valid E Data Valid E Data DZO OEZ OEA OEH MSM5416283 t RP "H" or "L" 16/40 ...
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... FSC CFH CWL CWL WCS WCH WCH MSM5416283 RSH CAS t RAL t t ASC CAH Column t t FSC CFH B t CWL WCS WCH ...
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... CWD CWD t t CAC CAC Out In Out In Out In Out OEZ OEZ t t OEA OEA MSM5416283 RSH CAS t RAL t t ASC CAH Column t t FSC CFH B t CWL t AWD CWD t CAC ...
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... Semiconductor RAS Only Refresh Cycle RAS t CRP CAS t t ASR RAH Address Row t t FSR RFH DSF WEL/U DQ0 - THS THH TRG RAS Open MSM5416283 RPC "H" or "L" 19/40 ...
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... CHR Inhibit Falling Transition t RAH A t RFH RWH C Open CBR Cycle Function Table CBR Refresh (Reset All Options CBR Refresh (Set STOP Address CBR Refresh (No Reset Options) MSM5416283 RPC "H" or "L" Function 20/40 ...
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... The type of CBR operations are determined by the logic states of "A", "B" and "C" RAS RSH t RAL t ASR t t ASC CAH Column t FHR t FSR t t FSC CFH t WSR t RCS t RRH t CAC RAC t OEA MSM5416283 t RAS t CHR t RAH A t RFH B t RWH C t OFF Valid Data t OEZ "H" or "L" 21/40 ...
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... CSH t RSH t CAS AR t RAL t t ASC CAH SAM Start t ASD t CSD Open t RSD TSD t SCP Note CQD Note 3 MSM5416283 TRP t SCC SCA t t SZS SCA SOH Data Out TQD Note 3 "H" or "L" 22/40 ...
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... QSF = "H"-- Upper SAM (256 - 511) is active RAS t CSH t RSH t CAS AR t RAL t t ASC CAH SAM Start t CTH t ATH Open RTH t t TSL TSD Data Out Data Out t TQD Note 2 MSM5416283 TRP t SCA t SOH Data Out Note 2 "H" or "L" 23/40 ...
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... RSH t CAS AR t RAL t t ASC CAH SAM Start Sj t CTH t ATH Open t RTH t SCC t t SCP STOP t SCA t SOH Data Out Data Out Note 2 MSM5416283 t RP STOP Data Out Data Out t SQD Note 2 "H" or "L" 24/40 ...
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... QSF = "H"-- Upper SAM (256 - 511) is active RAS t CSH t RSH t CAS AR t RAL t t ASC CAH SAM Start t CSD Open t RSD t SCP Note SDD t CQD Note 3 MSM5416283 SCC SDS SDH SDS SDH Data In Data In Note 3 "H" or "L" 25/40 ...
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... CSH t RSH t CAS AR t RAL t t ASC CAH SAM Start Sj t CTH t ATH Open t RTH t SCC t t SCP STOP SDS SDH SDH Data In Data In Note 2 MSM5416283 t RP STOP Data In Data In t SQD Note 2 "H" or "L" 26/40 ...
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... SCP SC t SDS SDQ0 - 15 Data In Data In t SEP t SCC SCP t t SEA Data t SEP SWH SWIS SWIH t SDH MSM5416283 t t SCA SCA t SOH SOH Data Out Data Out t SWS t SDS t t SZE SDH Data In Data In "H" or "L" 27/40 ...
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... PIN FUNCTIONS Address Input The 18 address bits decode 16 bits of the 4,194,304 locations in the MSM5416283 memory array. The address bits are multiplexed to 9 address input pins (A0 - A8) as standard DRAM. 9 row address bits are latched at the falling edge of RAS. The following 9 column address bits are latched at the falling edge of CAS ...
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... Serial Input/Output: SDQ0 - SDQ15 Serial input/output mode is determined by the most recent read or write transfer cycle. When a read transfer cycle is performed, the SAM port is in the output mode. When a write or pseudo write transfer cycle is performed, the SAM port is switched from output mode to input mode. MSM5416283 29/40 ...
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... OPERATION MODES Table-1 shows the function truth table for a listing of all available RAM ports, and transfer operations of the MSM5416283. The RAM port and data transfer operations are determined by the state of CAS, TRG, WEL, WEU and DSF at the falling edge of RAS, and by the level of DSF at the falling edge of CAS. ...
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... RAM PORT OPERATION Extended RAM Read Cycle: RAS falling edge --- TRG = CAS = "H", DSF = "L" The MSM5416283 offers an accelerated page mode cycle (EXTENDED PAGE MODE) by eliminating output disable from CAS "high", and it allows CAS precharge time (t without the output data becoming invalid. This new data out operates (Extended data out) as any RAM read or Page Mode Read, except data will be held valid after CAS goes " ...
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... Semiconductor Load/Read Color Register: RAS falling edge --- CAS = TRG = WEL = WEU = DSF = "H" The MSM5416283 is provided with an on-chip 16-bit color register for use during the flash write or block write operation. Each bit of the color register corresponds to one of the DRAM I/O blocks ...
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... Note : Location "*" can not be loaded. Example of Block Write MSM5416283 Bit 15 01110011 01101011 00111100 Upper Byte * * * * * * * * * * * * ...
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... SAM pointer moves to the TAP location selected for the second split SAM to shift data in or out sequentially, starts from this TAP location at the most significant bit (511 or 255), and finally wraps around to the least significant bit. TAP TAP 255 256 257 MSM5416283 511 34/40 ...
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... Semiconductor DATA TRANSFER OPERATIONS The MSM5416283 features two types of bidirectional data transfer capability between RAM and SAM. 1) Conventional (non split) transfer: 512 words by 16 bits of data can be loaded from RAM to SAM (Read transfer), or from SAM to RAM (Write transfer). 2) Split transfer: 256 words by 16 bits of data can be loaded from the lower/upper half of the RAM to the lower/upper half of the SAM (Split read transfer), or from the lower/upper half of SAM to the lower/upper half of RAM (Split write transfer) ...
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... AX8). WEL or WEU = "L" during the RAS cycle. A rising edge of the from the falling edge of the CAS, at which time CSD MSM5416283 from the rising SCA or V after the and t ...
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... Semiconductor Split Data Transfer and QSF The MSM5416283 features a bidirectional split data transfer capability between the RAM and SAM. During split data transfer operation, the serial register is split into two halves which can be controlled independently. Split read or split write transfer operation can be performed to or from one half of the serial register, while serial data can be shifted into or out of the other half of the serial register ...
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... Programmable SAM Stops in Split Transfer Cycle The MSM5416283 has a boundary split register operation using programmable stops CBRS cycle has been performed, the split transfer cycle performs the boundary operation. Figure 2 shows an example of a boundary split register (4 stop points). The stop points define a SAM location at which the access will change from one half of the SAM to the other half (at the TAP address) ...
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... Therefore recommended that the initial state be set (ex. Perform a CBRR cycle to select Non Persistent Write-per-bit mode) after the initialization of the device is performed and before valid operations begin. SAM Stop Boundary Table Address MSM5416283 Size of Partition 256 128 39/40 ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM5416283 (Unit : mm) Package material Epoxy resin ...