YSD917-M Yamaha, YSD917-M Datasheet

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YSD917-M

Manufacturer Part Number
YSD917-M
Description
YSD917-MStereo/Audio 
Manufacturer
Yamaha
Datasheet

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Outline
Features
• Sampling frequency : Two ranges are available including;
• Can select and provide various clocks to peripheral devices such as DAC and ADC as a master clock.
• Can supply clock to ADC and DAC in any case including when DAIF signal is not present.
• The device checks the DAIF signal at all times including when it supplies clock to ADC. Thus, it is capable
• Has a terminal that outputs a signal indicating the double rate operation.
• Every channel status and user data can be read through the microcomputer interface.
• Has an output terminal for interrupt that informs external devices of the changes of the status information.
• Can be adaptable to various serial data output formats by setting a register.
• The relationship between the word clock and data is maintained at all times including the moment of
• Two or more devices can be used synchronously when in the slave mode.
• Microcomputer interface with four wire serial system.
• Internal operating frequency of 25 MHz
• Power down mode
• Single power supply voltage of 5.0 V
• Si-gate CMOS process
• 28 pin SOP package (YSD917-M)
YSD917 is an LSI that receives and demodulates signals with the digital audio interface format that
conform to EIAJ CP1201 and IEC958 standards (hereafter referred to as “DAIF signal”).
This LSI can be used for to various application such as AV amplifiers because it is capable of accepting
DAIF signal which sampling frequency ranges from 32 kHz to 96 kHz and the demodulated serial data
output is capable of being selected from various formats.
of reading status information as necessary.
transfer from PLL unlock to lock or lock to unlock so that the effect of the transfer to peripheral devices
is suppressed.
[Fundamental Functions]
[Other features]
Digital Audio Interface Receiver 5
YSD917
32 kHz to 48 kHz (hereafter referred to as “normal rate”) and
64 kHz to 96 kHz (hereafter referred to as “double rate”)
DIR5
CATALOG No: LSI-4SD917A3
YSD917
2003.3

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YSD917-M Summary of contents

Page 1

... Two or more devices can be used synchronously when in the slave mode. [Other features] • Microcomputer interface with four wire serial system. • Internal operating frequency of 25 MHz • Power down mode • Single power supply voltage of 5.0 V • Si-gate CMOS process • 28 pin SOP package (YSD917-M) DIR5 YSD917 CATALOG No: LSI-4SD917A3 2003.3 ...

Page 2

... VSS MCK 11 18 VDD 12 17 SDO 13 16 SDBCK 14 15 < 28pin SOP Top View > YSD917 SDMCK SDBCK Output clock generation SDWCK ERR/BS DBL/V SYNC/U FS128/C Serial Conversion SDO detection SCK SI SO /CS VDD INT /LOCK ERR/BS DBL/V FS128/C ...

Page 3

... YSD917 Terminal Function List No. Name I/O 1 AVDD - Analog power supply for PLL (+5V) 2 PCO A PLL filter connection terminal 3 AVSS - Analog ground 4 M/S Is+ Master/slave mode selection 5 DDIN I Digital audio interface data input s 6 TEST I + Test terminal (To be open /IC I Initial clear input ...

Page 4

... Digital Audio Interface Format signal (DAIF signal) is inputted through this terminal . 4. Analog circuit for PLL: The capacitor for PLL is connected here. Connect a capacitor of 4700pF between the terminals PCO and AVSS. 4 XI, XO, MCK SDMCK ---------------------------------------------------- (1) LOCKMOD0 Normal rate 0 256fs 1 256fs - 256fs /IC PCO 4700pF YSD917 ----------------------------- (2) Double rate 256fs 128fs 12.288MHz –(3) ...

Page 5

... YSD917 5. Serial data interface: Supplies clocks to the peripheral devices such as DAC, ADC and DSP. The period of SDBCK, SDWCK and FS128 is obtained as follows by dividing the clock of SDMCK. • SDBCK ⇒ • SDWCK ⇒ • FS128 ⇒ In the slave mode, SDBCK and SDWCK are input terminals and FS128 and SYNC are fixed to “L”. ...

Page 6

... TEST is a terminal for testing the LSI. Keep it open when using this device /LOCK, ERR, DBL, INT /CS, SCK, SI, SO Address of register R High-Z Address of register R/W Don't Care High M/S, TEST YSD917 Write data Don't Care Don't Care High Read data ...

Page 7

... YSD917 Electrical Characteristics 1. Absolute maximum ratings Item Symbol Supply voltage V AV Input voltage Storage temperature T 2. Recommended operating conditions Item Symbol Supply voltage Operating temperature XI clock frequency 3. DC characteristics Condition: Under recommended operating conditions Item H level input voltage (1) H level input voltage (2) ...

Page 8

... Example of System Configuration DAIF (SPDIF) 24.576MHz Analog ADC 8 HOST PROCESSOR /LOCK ERR DBL DDIN YSD917 (DIR5 DSP YSD917 INT DAC ...

Page 9

... YSD917 External Dimensions of Package 9 ...

Page 10

... Matsunokijima, Toyooka-mura Iwata-gun, Shizuoka-ken, 438-0192, Japan Tel. +81-539-62-4918 Tokyo Office 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568, Japan Tel. +81-3-5488-5431 Osaka Office 3-12-12, Minami Senba, Chuo-ku, Osaka City, Osaka, 542-0081, Japan Tel. +81-6-6252-6221 YSD917 Fax. +81-539-62-5054 Fax. +81-3-5488-5088 Fax. +81-6-6252-6229 Printed in Japan ...

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