IC62LV256-45UI INTEGRATED CIRCUIT SOLUTION, IC62LV256-45UI Datasheet
IC62LV256-45UI
Related parts for IC62LV256-45UI
IC62LV256-45UI Summary of contents
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... IC62LV256 Document Title 32K x 8 Low Power SRAM with 3.3V Revision History Revision No History 0A Initial Draft The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. ...
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... Chip Enable (CE) input and an active LOW Output Enable (OE) input. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IC62LV256 is pin compatible with other 32K x 8 SRAMs in 300mil DIP and SOJ, 330mil SOP, and 8*13.4mm TSOP-1 packages. DECODER ...
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... IC62LV256 PIN CONFIGURATION 28-Pin DIP, SOJ and SOP A14 1 28 VCC A12 A13 A11 A10 I/O7 I/ I/O6 I/ I/O5 I/ I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS A0-A14 Address Inputs CE Chip Enable Input ...
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... IC62LV256 OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage ( Input Leakage LI I Output Leakage LO Notes – ...
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... IC62LV256 READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time OHA CE Access Time t ACE OE Access Time t DOE OE to Low-Z Output t (2) LZOE OE to High-Z Output t (2) HZOE CE to Low-Z Output t (2) LZCE CE to High-Z Output ...
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... IC62LV256 AC WAVEFORMS READ CYCLE NO. 1 (1,2) ADDRESS D OUT READ CYCLE NO. 2 (1,3) ADDRESS OUT SUPPLY CURRENT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE Address is valid prior to or coincident with CE LOW transitions OHA ...
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... IC62LV256 WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End t SCE t Address Setup Time to Write End AW t Address Hold from Write End HA t Address Setup Time SA WE Pulse Width t (4) PWE t Data Setup to Write End SD t Data Hold from Write End ...
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... IC62LV256 CE Controlled WRITE CYCLE NO. 2 (CE ADDRESS OUT D IN Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write ...
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... Integrated Circuit Solution Inc. ALSR007-0A 10/5/2001 ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 45 IC62LV256-45JI 300mil SOJ 45 IC62LV256-45TI 8*13.4mm TSOP-1 45 IC62LV256-45UI 330mil SOP 70 IC62LV256-70JI 300mil SOJ 70 IC62LV256-70TI 8*13.4mm TSOP-1 70 IC62LV256-70UI 330mil SOP 100 IC62LV256-100JI 300mil SOJ 100 IC62LV256-100TI 8*13 ...