IP101ALF ETC-unknow, IP101ALF Datasheet
IP101ALF
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IP101ALF Summary of contents
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Single port 10/100 Fast Ethernet Transceiver Features 10/100Mbps TX Full-duplex or half-duplex Supports Auto MDI/MDIX function Fully compliant with IEEE 802.3/802.3u Supports IEEE 802.3u auto-negotiation Supports MII / RMII / SNI interface IEEE 802.3 full duplex control specification Supports Automatic ...
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Table Of Contents Features................................................................................................................................................... 1 General Description ................................................................................................................................. 1 Table Of Contents .................................................................................................................................... 2 Revision History....................................................................................................................................... 3 Transmit and Receive Data Path Block Diagram .................................................................................... 4 Pin Assignments ...................................................................................................................................... 5 1 Pin Descriptions................................................................................................................................ 6 Pin Descriptions (continued).................................................................................................................... 7 Pin Descriptions ...
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Revision History Revision # IP101A LF-DS-R01 Initial release. IP101A LF-DS-R02 Add Crystal Specification and MII AC Timing. IP101A LF-DS-R03 Modify 7.1.2 Power Dissipation in page 41. IP101A LF-DS-R04 Modify register 5.11 in page 16. IP101A LF-DS-R05 Add the order information ...
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Transmit and Receive Data Path Block Diagram TXD 100Mbps 4B/5B Encoder 100Mbps Scrambler 5B 100Mbps Mux 100Mbps Parallel to Serial 100Mbps NRZI/MLT-3 Encoder 100Mbps D/A & Line Driver TXO Copyright © 2004, IC Plus Corp. MII/SNI/RMII Interface 100Mbps 4B/5B Decoder ...
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Pin Assignments 37. AN_ENA 38. DPLX 39. SPD 40. RPTR 41. APS 42. RESET_N 43. ISOL Fast Ethernet Single Phy Transceiver Chip 44. MII_SNIB 45. DGND 46. X1 47. X2 48. INTR Copyright © 2004, IC Plus Corp. IP101A LF ...
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Pin Descriptions Type Description LI Latched Input in power up or reset I/O Bi-directional input and output I Input O Output Pin no. Label MII and PCS Interface - Management Interface Pins 25 MDC 26 MDIO MII and PCS ...
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Pin Descriptions (continued) Pin no. Label MII and PCS Interface – Media Independent Interface (MII) Pins 24 RX_ER 1 COL/RMII 23 CRS/LEDMOD Copyright © 2004, IC Plus Corp. Type O Receive error: This pin outputs a high status when errors ...
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Pin Descriptions (continued) Pin no. Label RMII (Reduced MII) 7 REF_CLK 16 C50M_O 2 TX_EN 5,6 TXD[1:0] 24 RX_ER 22 CRS_DV 20, 21 RXD[1:0] SNI (Serial Network Interface): 10Mbps only 2 TX_EN 7 TX_CLK 6 TXD0 16 RX_CLK 21 RXD0 ...
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Pin Descriptions (continued) Pin no. Label IC Configuration Options 43 ISOL 40 RPTR 39 SPD 38 DPLX 37 AN_ENA 41 APS 44 MII_SNIB Copyright © 2004, IC Plus Corp. Type I Set high to this pin will isolate IP101A LF ...
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Pin Descriptions (continued) Pin no. Label LED and PHY Address Configuration These five pins are latched into the IP101A LF during reset to configure PHY address [4:0] used for MII management register interface. And then, in normal operation after initial ...
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Pin Descriptions (continued) Pin no. Label Clock and Miscellaneous - Crystal Input/Output Pins Clock and Miscellaneous - Miscellaneous Pins 42 RESET_N INTR 48 27 TEST_ON 28 ISET Copyright © 2004, IC Plus Corp. Type Description O ...
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Pin Descriptions (continued) Pin no. Label Power and Ground 32 REGOUT 36 AVDD33 29,35 AGND 8 REGIN 14 DVDD33 11,17,45 DGND Copyright © 2004, IC Plus Corp. Type Description P Regulator Power Output: This is a regulator power output for ...
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Register Descriptions Bit Name Register 0 : MII Control Register 15 Reset When set, this action will bring both status and control registers of the PHY to default state. This bit is self-clearing Software reset 0 = ...
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Register Descriptions (continued) Bit Name Register 1 : MII Status Register 15 100Base- enable 100Base-T4 support 0 = suppress 100Base-T4 support 14 100Base- enable 100Base-TX full duplex support Full Duplex 0 = suppress 100Base-TX full duplex ...
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Register Descriptions (continued) Bit Name Register 2 : PHY Identifier Register 1 15:0 PHYID1 PHY identifier ID for software recognize IP101A LF Bit Name Register 3 : PHY Identifier Register 2 15:0 PHYID2 PHY identifier ID for software recognize Note ...
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Register Descriptions (continued) Register 4 lists the advertised abilities during auto-negotiation for what will be transmitted to IP101A LF’s Link Partner. Bit Name Register 4 : Auto-Negotiation Advertisement Register 15 NP Next Page bit transmitting the primary capability ...
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Register Descriptions (continued) This register contains the advertised abilities of the Link Partner as received during Auto-negotiation. The content changes after the successful Auto-negotiation if Next-pages are supported. Bit Name Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR) 15 Next ...
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Register Descriptions (continued) Register 6 defines more auto-negotiation registers to meet the requirement. Bit Name Register 6 : Auto-Negotiation Expansion Register 15:5 Reserved This bit is always set MLF This status indicates if a multiple link fault ...
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Register Descriptions (continued) Bit Name Register 16 : PHY Spec. Control Register 15 Debug Mode 0 = IP101A LF operates at normal mode 1 = IP101A LF operates at debug mode (Note: the functionalities of bit 16:<14:12>, and 16:<4:0> depend ...
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Register Descriptions (continued) Bit Name Register 17 : PHY Interrupt Ctrl/Status Register 15 INTR pin used Set high to enable pin48 as an interrupt pin. Pin48 will be high impedance if this bit is set low. 14:12 Reserved 11 All ...
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Functional Description IP101A LF 10/100Mbps Ethernet PHY Transceiver integrates 100 Base-TX and 10 Base-T modules into a single chip. IP101A LF acts as an interface between physical signaling and Media Access Controller (MAC). IP101A LF has several major functions: ...
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NRZ format. 5. Clock Recovery: The receiver circuit recovers data from the input stream by regenerating clocking information embedded in the serial stream. The clock recovery block extracts the RXCLK from the transition of received 6. DSP Engine: This block ...
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MDC, Management Data Clock, provides management data clock at maximum of 10MHz as a reference for MDIO, Management Data Input/Output. CRS, Carrier Sense, is used for signaling data transmission is in process while COL, Collision, is used for signaling the ...
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Auto-Negotiation and Related Information IP101A LF supports clause 28 in the IEEE 802.3u standard. IP101A LF can be operated either in 10Mbps/100Mbps or half/full duplex transmission mode. IP101A LF also supports flow control mechanism to prevent any collision in the ...
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Auto MDIX function IP101A LF will keep sensing incoming signal in MDI RX pair incoming signal is detected, IP101A LF will switch TX and RX pairs automatically trying to establish connection. IP101A LF supports this function both in ...
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Flexible Clock Source Pin1 Pin44 COL/RMII MII/SNIB 1 1 RMII, ext 50MHz osc clk in to pin7 1 0 RMII, 25MHz crystal or osc from X1,X2; 50MHz clk out to pin16. (Please refer to the following figure for our recommened ...
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Power-Down Modes IP101A LF can be power-down by 4 methods. These 4 methods are as follow: Power Down in bit 11 of Register 0: Enable this bit will disconnect the power to IP101A LF and also internal clock, but MDC ...
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Serial management interface User can access IP101A LF’s MII registers through serial management interface MDC and MDIO. A specific pattern on MDIO is used to access a MII register. Its format is shown in the following table. When the ...
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Crystal Specifications Item 1 Nominal Frequency 2 Oscillation Mode 3 Frequency Tolerance at 25š 4 Temperature Characteristics 5 Operating Temperature Range 6 Equivalent Series Resistance 7 Drive Level 8 Load Capacitance 9 Shunt Capacitance 10 Insulation Resistance 11 Aging ...
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Layout Guideline General Layout Guideline Best performance depends on good layout. The following recommendation steps will help customer to gain maximum performance. Create good power source to minimize noise from switching power source. All components are qualified, especially high ...
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Electrical Characteristics 7.1 D.C. Characteristic 7.1.1 Absolute Maximum Rating Symbol Supply Voltage Storage Temp 7.1.2 Power Dissipation Symbol Auto Power Saving Mode Analog off Mode Power Down Mode Isolate Mode 100 Full 100 Half 10 Full 10 Half 10 ...
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A.C. Characteristic 7.2.1 MII Timing a. Pin Reset and Clock output timing relationship Symbol T Delay time after reset to clock output delay RESET_N MII_TXCLK MII_RXCLK b. Transmit Timing Requirements Symbol T Transmit clock period 100M MII TxClk T ...
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RMII Timing a. Pin Reset and Clock output timing relationship (If pin 16 has been configured as 50MHz output ) Symbol T Delay time after reset to clock output delay RESET_N C50M_O b. Clock Timing RMII Symbol Description T ...
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REFCLK RXD[1:0] RX_ER CRS_DV RXD[1:0] RX_ER CRS_DV T d. RMII Transmit Timing Symbol T TXD[1:0], TX_EN, Data Setup to REFCLK rising SU_TXD_RMII edge T TXD[1:0], TX_EN, Data Hold from REFCLK HD_TXD_RMII rising edge REFCLK TX[1:0] TX_EN 7.2.3 SMI Timing a. ...
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T MDIO setup time mh T MDIO hold time Order Information Part No. IP101A 48-PIN LQFP IP101A LF 48-PIN LQFP Copyright © 2004, IC Plus Corp. ...
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Package and Mechanical Specification SEATING PLANE Notes: 1. DIMENSION D & NOT INCLUDE MOLD FLASH OR PROTRUSION. 2. DIMENSION b DOES NOT ...