FAS368M QLogic Corporation, FAS368M Datasheet

no-image

FAS368M

Manufacturer Part Number
FAS368M
Description
Manufacturer
QLogic Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FAS368M
Manufacturer:
QLOGIC
Quantity:
1 831
Part Number:
FAS368M
Manufacturer:
QLOGIC
Quantity:
20 000
Part Number:
FAS368M 2406357
Manufacturer:
QLOGIC
Quantity:
20 000
Part Number:
FAS368M2405140
Manufacturer:
QLOGIC
Quantity:
8
Features
Product Description
architecture SCSI processor (FAS) chip family. The
FAS368M supports internal multimode LVD and
single-ended (SE) transceivers, which allow the chip to
support LVD and SE operations in initiator and target roles.
and peripheral applications. To ensure firmware
compatibility and provide FAS366U customers a seamless
upgrade path, the FAS368M uses the same SCSI core,
foundry, and process as the FAS366U. Note that the
53368-580-00 A
The FAS368M is a new addition to the QLogic fast
The FAS368M is a single-chip controller for use in host
FAS368M Fast Architecture SCSI Processor
Compliance with ANSI X3T10/1142D SCSI
Parallel Interconnect-2 (SPI-2) standard
Compliance with ANSI SCSI configured
automatically (SCAM) protocol levels 1 and 2
Sustained SCSI data transfer rates of up to:
Synchronous DMA timing; DMA speed of
50 Mbytes/sec
REQ and ACK programmable assertion and
deassertion control
Support for hot plugging
Target and initiator block transfer sequences
Bus idle timer
Split-bus architecture
Pipelined command structure
On-chip, single-ended SCSI transceivers
(48-mA drivers)
On-chip, multimode, low voltage differential
(LVD) drivers
On-chip differential sense decoder
Initiator and target roles
Active negation
16-bit recommand counter
Differential mode
SCSI bus reset watchdog timer
40 Mbytes/sec synchronous (Ultra and wide
SCSI)
14 Mbytes/sec asynchronous (wide SCSI)
QLogic Corporation
Data Sheet
FAS368M package size, pin out, and transceivers differ
from the FAS366U. The FAS368M block diagram is shown
in figure 1.
and initiator block transfer sequences. The block sequences
reduce firmware overhead and are composed of the
following new commands: Target Block Sequence
(including the bus idle timer), Initiator Block Sequence,
Load/Unload Block Registers sequences, Abort Block
Sequence, and Disconnect Abort Block Sequence.
differential mode SCSI operations and operates in initiator
and target roles. The FAS368M has been optimized for
interaction with a DMA controller and the controlling
microprocessor.
microprocessor and DMA bus configurations. A separate
8-bit microprocessor bus (PAD) provides access to all
internal registers, and a 16-bit DMA bus (DB) provides a
path for DMA transfers through the FIFO. Each bus is
protected by a parity bit (byte-wide parity) to improve data
integrity. During data transfer, the microprocessor has
instant access to status and has the ability to execute
commands.
SCAM Implementation
protocol. Refer to the latest revision of X3T10/855D,
Annex B. The SCAM protocol requires direct access and
control over the SCSI data bus and several of the SCSI
phase and control signals. The majority of the SCAM
protocol can be implemented in firmware at
microprocessor speeds. The following SCAM features are
supported in the hardware:
The FAS368M implements QLogic’s new SCSI target
The FAS368M supports both single-ended and
The versatile split-bus architecture supports various
The FAS368M supports levels 1 and 2 of the SCAM
Arbitration without an ID
Slow response to selection with an unconfirmed ID
Detection of and response to SCAM selection
FAS368M
1

Related parts for FAS368M

FAS368M Summary of contents

Page 1

... FAS368M supports internal multimode LVD and single-ended (SE) transceivers, which allow the chip to support LVD and SE operations in initiator and target roles. The FAS368M is a single-chip controller for use in host and peripheral applications. To ensure firmware compatibility and provide FAS366U customers a seamless upgrade path, the FAS368M uses the same SCSI core, foundry, and process as the FAS366U ...

Page 2

... The DREQ signal initiates DMA transfers and runs asynchronous to the user’s clock. For read operations, DACK acts as a chip select to enable the FAS368M drivers onto the DMA bus. The chip select role of DACK helps support the burst timing of fast DMA mode. DACK selects the FAS368M after DREQ is asserted and is removed either after DREQ is deasserted or when the DMA transfer is paused ...

Page 3

... QLogic Corporation Table 1. DMA Interface Signals (Continued) Pin Type Active Level DBWR I Rising edge The trailing edge strobes data into the FAS368M FIFO on DMA write operations. DB15-0 I/O N/A This is the DMA data bus. Table 2. DMA Timing Symbol Description t1 DBRD/DBWR low to DREQ low ...

Page 4

... Interfaces The FAS368M interfaces consist of the microprocessor bus and the SCSI bus. Pins that support these interfaces and other chip operations are shown in figure 4. 4 MICROPROCESSOR INTERFACE 8 DMA AND 16 MICROPROCESSOR INTERFACE 2 RESET POWER AND GROUND Figure 4. FAS368M Functional Signal Grouping 4 FAS368M ...

Page 5

... QLogic Corporation Packaging The FAS368M is available in a 144-pin thin quad flat pack (TQFP). The mechanical drawings are illustrated in figure 3. 22.0 PIN 108 20.0 PIN 109 22.0 0.4 20.0 0.2 INDEX MARK PIN 144 PIN 1 NOTE: ALL DIMENSIONS ARE IN MILLIMETERS. ALL DIMENSIONS ARE NOMINAL UNLESS SPECIFIED OTHERWISE. Electrical Characteristics ...

Page 6

... FAS368M QLogic Corporation 53368-580-00 A ...

Page 7

... QLogic Corporation 53368-580-00 A FAS368M 7 ...

Page 8

... All other brand and product names are trademarks or registered trademark of their respective holders. ©January 30, 1998 QLogic Corporation, 3545 Harbor Blvd., Costa Mesa, CA 92626, (800) ON-CHIP-1 or (714) 438-2200 8 FAS368M Specifications are subject to change without notice. QLogic is a trademark of QLogic Corporation. QLogic Corporation ...

Related keywords