WT62P1 Weltrend, WT62P1 Datasheet
WT62P1
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WT62P1 Summary of contents
Page 1
... GENERAL DESCRIPTION The WT62P1 is a microcontroller for digital controlled monitor with Universal Serial Bus (USB) interface. It contains an 8-bit CPU, 32K bytes flash memory, 512 bytes RAM, 14 PWMs, parallel I/Os, SYNC signal processor, timer, DDC1/2B interface, master/slave I A/D converter and watch-dog timer. FEATURES 8-bit 6502 compatible CPU with 6MHz operating frequency ...
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... PA2/PWM8 PB4/SCL2 14 PA1/SCL1 PA0/SDA1 PC0/AD0 PC1/AD1 PC2/AD2 Page 3 WT62P1 Data Sheet Rev. 1.01 40-pin PDIP 40 VIN 39 HIN 38 PWM3 37 PD5/PWM4 36 PD4/PWM5 35 PD3/PWM6 34 PD2/PWM7 33 PD1/HOUT 32 PD0/VOUT WT62P1-N40 31 PA7/PWM13/CLAMP 30 PA6/PWM12 29 PA5/PWM11 28 PA4/PWM10 27 PA3/PWM9 26 PA2/PWM8 25 PA1/SCL1 24 PA0/SDA1 23 PC0/AD0 22 PC1/AD1 21 PC2/AD2 28-pin Skinny PDIP 28 PA4/PWM10 27 PA3/PWM9 26 PA2/PWM8 ...
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... I/O Port A7 or PWM13 output or clamp pulse output. I/O Port D0 or Vsync output. I/O Port D1 or Hsync output. I/O Port D2 or PWM7 output. I/O Port D3 or PWM6 output. No Connection. I/O Port D4 or PWM5 output. I/O Port D5 or PWM4 output. I/O PWM3 output (10V open-drain). I Hsync Input. I Vsync input. I/O USB D- signal. Page 4 WT62P1 Data Sheet Rev. 1.01 ...
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... System Reset There are four reset sources of this controller. Fig.1 shows the block diagram of reset logic. Weltrend Semiconductor, Inc. Registers Reserved 128 bytes RAM Reserved 384 bytes RAM Reserved Reserved Flash ROM Page 5 WT62P1 Data Sheet Rev. 1.01 ...
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... When VDD is below 3.9V, an internal reset signal is generated. The reset signal will last 2.048 ms after the voltage is higher than 3.9V. Watchdog Timer Reset If a time-out happens when watchdog timer is enabled, a reset pulse is generated. Please refer watchdog timer section for more information. Weltrend Semiconductor, Inc. Fig. 1 Reset Signals Page 6 WT62P1 Data Sheet Rev. 1.01 %&' & % ) !"#$ ...
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... DATA[2] READ_PA_DATA DATA[2] Weltrend Semiconductor, Inc. PA0OE D Q WRITE_PA_CTRL RESET PA0 D Q WRITE_PA_DATA RESET Fig.2 Structure of PA0 and PA1 PA2OE D Q WRITE_PA_CTRL RESET PA2 D Q WRITE_PA_DATA RESET Fig.3 Structure of PA2 Page 7 WT62P1 Data Sheet Rev. 1.01 PA0 PA2 ...
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... Bit 6 Bit 5 Bit4 -- -- PB5OE PB4OE Description Bit 7 Bit 6 Bit 5 Bit4 -- -- PB5 PB4 -- -- PB5 PB4 Description Page 8 WT62P1 Data Sheet Rev. 1.01 Bit 3 Bit 2 Bit 1 Bit 0 PA3OE PA2OE PA1OE PA0OE Bit 3 Bit 2 Bit 1 Bit 0 PA3 PA2 PA1 PA0 PA3 PA2 PA1 PA0 Bit 3 ...
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... Bit 6 Bit 5 Bit4 -- -- PD5OE PD4OE Description Bit 7 Bit 6 Bit 5 Bit4 -- -- PD5 PD4 -- -- PD5 PD4 Description Page 9 WT62P1 Data Sheet Rev. 1.01 Bit 3 Bit 2 Bit 1 Bit 0 PC3OE PC2OE PC1OE PC0OE Bit 3 Bit 2 Bit 1 Bit 0 PC3 PC2 PC1 PC0 PC3 PC2 PC1 PC0 Bit 3 ...
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... H Period Counter SEPART MUX EXTRHS Composite Signal BYPASS Separator EXTRVS MUX FREEHS FREEVS SEPART MUX Test Pattern Generator Page 10 WT62P1 Data Sheet Rev. 1.01 H Freq Counter ENFREE HOPOL MUX H Polarity Control HOUT Clamp Pulse CLAMP Generator ENFREE VOPOL VOUT MUX V Polarity Control ...
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... Bit 6 Bit 5 Bit4 HINPOL -- HFL4 HFH6 HFH5 HFH4 Description Min. Freq HFH6..0 $40h $40h $51h $51h Page 11 WT62P1 Data Sheet Rev. 1.01 Bit 3 Bit 2 Bit 1 Bit 0 HFL3 HFL2 HFL1 HFL0 HFH3 HFH2 HFH1 HFH0 QUICK=”1” HFL4..0 Max. Freq Min. Freq $0000xb 64 ...
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... HPRD7..0 Max. Freq $7Ch 48.78KHz 80KHz $7Dh 48.387KHz $7Eh 48KHz 63.83KHz $BFh 31.579KHz $C0h 31.414KHz 62.5KHz $C1h 31.25KHz Page 12 WT62P1 Data Sheet Rev. 1.01 Bit 3 Bit 2 Bit 1 Bit 0 VF3 VF2 VF1 VF0 VF11 VF10 VF9 VF8 Min. Freq 64.969Hz 64.935Hz 64.901Hz 59.981Hz 59 ...
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... H XOR V Bypass H pulse EXTRHS EXTRVS Hsync Vsync H EORV Bypass H pulse EXTRHS EXTRVS Fig. 6 Timing relationship of composite sync signal separator Weltrend Semiconductor, Inc. Insert H pulse 2us 2us 5.5~6.5us Insert H pulse 2us 2us 5.5~6.5us Page 13 WT62P1 Data Sheet Rev. 1.01 Bypass H pulse Bypass H pulse ...
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... 41.67ns 41.67ns Page 14 WT62P1 Data Sheet Rev. 1.01 PAT1 = 1 , PAT0 = 1 011 110 111 81.25KHz 90.909KHz 106.195KHz 64.865Hz 84.8Hz 84.96Hz 12.333us 11us 9.417us 15.417ms 11.792ms 11.771ms 1.083us 1us 0.833us 1.833us 1.583us 1 ...
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... Clamp pulse follows HOUT signal’s falling edge. Weltrend Semiconductor, Inc. Bit 6 Bit 5 Bit4 Bit 3 VOPOL QUICK SEPART ENFREE CLPEG CLPPO CLPPW FREE1 -- -- -- -- Description Page 15 WT62P1 Data Sheet Rev. 1.01 0.542~0.625us/2.042~2.125us 0.542~0.625us/2.042~2.125us Bit 2 Bit 1 Bit 0 ENPAT FREE0 PAT1 PAT0 SOG FREE2 BYPASS ...
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... Composite sync signal comes from HIN pin. BYPASS Select bypass the composite signal separator or not. “ 1” : HOUT pin outputs sync signal bypass the composite signal separator. “ 0” : HOUT pin outputs sync signal from the composite signal separator. Weltrend Semiconductor, Inc. Data Sheet Rev. 1.01 Page 16 WT62P1 ...
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... HLFO pin outputs same frequency from HLFI pin. HF_POL “ 1” : HLFO polarity is not same as HLFI. “ 0” : HLFO polarity is same as HLFI. Weltrend Semiconductor, Inc Fig. 10 Half Hsync frequency Bit 6 Bit 5 Bit4 -- -- -- -- Bit Description Page 17 WT62P1 Data Sheet Rev. 1.01 HLFO Bit 3 Bit 2 Bit 1 Bit 0 -- ENHFIO HALF HF_POL ...
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... DDC_AR0 register (to release the SCL1 pin). The host will output ACK after received a data byte. When host wants to finish reading, it outputs NACK to stop communication. Program can read the RXACK1 bit to check the acknowledge bit that host sends. Weltrend Semiconductor, Inc interface with DDC1 function compatible with VESA D7,D6,...., D0 A Page 18 WT62P1 Data Sheet Rev. 1.01 D7,D6,...., ...
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... Weltrend Semiconductor, Inc N N N START N Page 19 WT62P1 Data Sheet Rev N START Pull low SCL Pull low SCL ...
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... Pull low Pull low SCL SCL A A Page 20 WT62P1 Data Sheet Rev. 1.01 Pull low STO SCL P A Pull low STO SCL ...
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... DTX3 Description Bit 6 Bit 5 Bit4 Bit 3 DDC2 FIRST STOP Description Bit 6 Bit 5 Bit4 Bit 3 DDC2 -- -- Description Page 21 WT62P1 Data Sheet Rev. 1.01 Bit 2 Bit 1 Bit 0 DRX2 DRX1 DRX0 Bit 2 Bit 1 Bit 0 DTX2 DTX1 DTX0 Bit 2 Bit 1 Bit 0 DDC2RW MATCH RXNAK1 Bit 2 Bit 1 ...
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... Enable DAR17- DAR11 to be compared when this bit is set. Weltrend Semiconductor, Inc. Bit 6 Bit 5 Bit4 Bit 3 DAR06 DAR05 DAR04 -- Description Bit 6 Bit 5 Bit4 Bit 3 DAR16 DAR15 DAR14 DAR13 Description Page 22 WT62P1 Data Sheet Rev. 1.01 Bit 2 Bit 1 Bit ENAR0 Bit 2 Bit 1 Bit 0 DAR12 DAR11 ENAR1 ...
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... DDC Flow Chart Weltrend Semiconductor, Inc Page 23 WT62P1 Data Sheet Rev. 1.01 ...
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... If a read command is received (SRW bit=1), write data to I2C_TX register, clear I2CRW bit and write I2C_ADR register to clear I2CRDY bit and stop pulling low the SCL2 pin for master sending out clock The received acknowledge bit is stored in RXNAK2 bit. Weltrend Semiconductor, Inc. Data Sheet Rev. 1. devices in the monitor such Page 24 WT62P1 ...
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... Page 25 WT62P1 Data Sheet Rev. 1.01 ...
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... Page 26 WT62P1 Data Sheet Rev. 1.01 ...
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... Bit 3 MTX6 MTX5 MTX4 MTX3 MRX6 MRX5 MRX4 MRX3 Bit 6 Bit 5 Bit4 Bit 3 SAR6 SAR5 SAR4 SAR3 Description Page 27 WT62P1 Data Sheet Rev. 1.01 Bit 2 Bit 1 Bit 0 SRW RXNAK2 I2CRDY Bit 2 Bit 1 Bit 0 I2CRW TXNAK2 SLAVE Bit 2 Bit 1 Bit 0 MTX2 MTX1 MTX0 ...
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... Master I C Flow Chart Weltrend Semiconductor, Inc. Page 28 WT62P1 Data Sheet Rev. 1.01 ...
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... Master I C (restart mode) Flow Chart Weltrend Semiconductor, Inc. Page 29 WT62P1 Data Sheet Rev. 1. ...
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... Slave I C Flow Chart )* '( #$% ! " Weltrend Semiconductor, Inc. "& ! " Page 30 WT62P1 Data Sheet Rev. 1.01 " ...
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... TIM5 ~ TIM0 Timer period = time base x (6-bit data) Weltrend Semiconductor, Inc. TIM0 TIM1 TIM2 TIM3 TIM4 TIM5 6-Bit Timer IE_TMR Fig.11 Block diagram of Timer Bit 6 Bit 5 Bit4 PS0 TIM5 TIM4 Bit Description Page 31 WT62P1 Data Sheet Rev. 1.01 IF_TMR Bit 3 Bit 2 Bit 1 Bit 0 TIM3 TIM2 TIM1 TIM0 ...
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... Bit 6 Bit 5 Bit4 -- AD5 AD4 Bit Description Bit 6 Bit 5 Bit4 -- -- -- Bit Description Resistor Array 6-bit Counter Fig.12 Block diagram of ADC Page 32 WT62P1 Data Sheet Rev. 1.01 Bit 3 Bit 2 Bit 1 Bit 0 AD3 AD2 AD1 AD0 Bit 3 Bit 2 Bit 1 Bit 0 CH3 CH2 CH1 CH0 ...
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... A/D Converter Flow Chart Weltrend Semiconductor, Inc. Page 33 WT62P1 Data Sheet Rev. 1.01 ...
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... Set CLR_INT in USB_FPC register and clear. Set CLR_INT in USB_FPC register and clear. Clear Interrupt Read HFREQ_H Register. Clear Interrupt Write a value to TIMER register Clear Interrupt Set CLRIRQ bit in IRQ_CON register and clear it . Clear Interrupt Set CLRVSO bit in IRQ_CON register and clear it . Page 34 WT62P1 ...
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... Bit Description Bit 6 Bit 5 Bit4 Bit Description Bit 6 Bit 5 Bit4 -- -- -- SYNC Bit Description Bit 6 Bit 5 Bit4 -- -- -- -- Bit Description Page 35 WT62P1 Data Sheet Rev. 1.01 Bit 3 Bit 2 Bit 1 Bit 0 IF_IRQ IF_VSO -- Bit 3 Bit 2 Bit 1 Bit 0 IE_IRQ IE_VSO -- Bit 3 Bit 2 Bit 1 Bit 0 TIMER IRQ ...
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... Disable Watchdog Timer. “ 0” : Enable Watchdog Timer. WDT “ 1” : Watchdog Timer reset period is 518.144ms +8.096ms. “ 0” : Watchdog Timer reset period is 259.072ms +8.096ms. Function Configuration Register This register controls the special configuration of WT62P1. Name Addr R/W Initial Bit 7 OPTION 0FFFh W ...
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... Tosc 2 Tosc PWM=00001001 32 Tosc 4 Tosc 4 Tosc PWM=00010010 Weltrend Semiconductor, Inc. Frame 2 Frame 3 Frame 4 2 Tosc 2 Tosc 4 Tosc 6 Tosc 4 Tosc 4 Tosc 256 Tosc Fig. 13 PWM output waveform Page 37 WT62P1 Data Sheet Rev. 1.01 Frame 5 Frame 6 Frame 7 2 Tosc 2 Tosc 2 Tosc 4 Tosc 6 Tosc 4 Tosc ...
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... PWM11 PWM12 PWM12 PWM12 PWM13 PWM13 PWM13 EPWM13 EPWM12 EPWM11 EPWM10 EPWM9 EPWM8 Description Page 38 WT62P1 Data Sheet Rev. 1.01 Bit 3 Bit 2 Bit 1 PWM0 PWM0 PWM0 PWM0 PWM1 PWM1 PWM1 PWM1 PWM2 PWM2 PWM2 PWM2 ...
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... USB address and endpoint decoding USB endpoint level flow control Maintain state of data toggle bits Interface to CPU Weltrend Semiconductor, Inc. VDD 3.3V Regulator Serial Interface Engine Interface Logic Data Bus Page 39 WT62P1 Data Sheet Rev. 1.01 EP0 OUT FIFO EP0 IN FIFO EP1 IN FIFO ...
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... The FIFO is used to buffer USB data. There are three FIFOs : Endpoint 0 has IN FIFO (transmit) and OUT FIFO (receive), Endpoint 1 has IN FIFO only. Each FIFO has 8 bytes depth. The architecture of FIFO is show as blow. DATA IN Write Pointer Weltrend Semiconductor, Inc. Data Sheet Rev. 1. DATA OUT Read Pointer Page 40 WT62P1 ...
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... ENRST ENSTAL0 ENOK0 Description Bit 6 Bit 5 Bit4 STALL1 EP1OK RESET Description Bit 7 Bit 6 Bit 5 Bit4 F0D7 F0D6 F0D5 F0D4 Description Page 41 WT62P1 Data Sheet Rev. 1.01 Bit 3 Bit 2 Bit 1 Bit 0 UAD3 UAD2 UAD1 UAD0 Bit 3 Bit 2 Bit 1 Bit 0 ENOUT ENSUP Bit 3 Bit 2 Bit 1 ...
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... CLRACT CLRINT REP0RP REP0WP REP1RP REP1WP Description Bit 6 Bit 5 Bit4 -- -- OUT0STL ENOUT0 IN0STL Description Bit 7 Bit 6 Bit 5 Bit4 F1D7 F1D6 F1D5 F1D4 Description Page 42 WT62P1 Data Sheet Rev. 1.01 Bit 3 Bit 2 Bit 1 Bit 0 UCNT3 UCNT2 UCNT1 UCNT0 Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 EP0VAL EP0TOG ...
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... Set EP1-IN FIFO ready to send data when this bit is “ 1” . EP1TOG Set data packet type of EP1-IN pipe. When this bit is “ DATA1. Weltrend Semiconductor, Inc. Bit 6 Bit 5 Bit4 -- -- -- -- Descriptions Page 43 WT62P1 Data Sheet Rev. 1.01 Bit 3 Bit 2 Bit 1 Bit 0 ENEP1 EP1STL EP1VAL EP1TOG ...
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... Reset Voltage RESET DD Weltrend Semiconductor, Inc. Min. -0.3 -0.3 -25 -10 Condition Min. 4.5 3.0 0.7V DD -0.3 2.2 -0.3 2.2 -0 -6mA 6mA <V < 12MHz, No load OSC 3.6 Page 44 WT62P1 Data Sheet Rev. 1.01 Max. Units 7.0 V VDD+0 125 Typ. Max. Units 5 5.5 V 3 ...
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... DDC1 Timing Symbol Parameter t SDA1 output valid from VSYNC rising edge VAA,DDC1 SDA1 Bit 0 (LSB) VSYNC Weltrend Semiconductor, Inc. t LOW,SYNC Null Bit Page 45 WT62P1 Data Sheet Rev. 1.01 Min. Typ. Max. Units 167 - - 167 - - Min. Typ. Max. Units 167 - - 167 - - Min. Typ. ...
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... Set-up time for DATA output t SCL1 and SDA1 rise time RISE,DDC t SCL1 and SDA1 fall time FALL.DDC t Set-up time for STOP condition SU,STOP SDA1 SCL1 Weltrend Semiconductor, Inc Page 46 WT62P1 Data Sheet Rev. 1.01 Min. Typ. Max. Units 0 - 100 kHz ...
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... Symbol t D+ and D- Rise Time RISE,USB t D+ and D- Fall Time FALL,USB t D+ and D- Rise/Fall Time Matching RFM V Crossover point CROSS RISE,USB Weltrend Semiconductor, Inc. Parameter t RISE,USB Page 47 WT62P1 Data Sheet Rev. 1.01 Min. Typ. Max. Units 75 300 ns 75 300 ns 70 130 % 1.3 2.0 V ...
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... TYPICAL APPLICATION CIRCUIT Crystal Oscillator Reset Pin and 3.3V Regulator PWM Output Weltrend Semiconductor, Inc. Data Sheet Rev. 1.01 Page 48 WT62P1 ...
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... Hsync, Vsync and DDC Interface Protection Weltrend Semiconductor, Inc. Data Sheet Rev. 1.01 Page 49 WT62P1 ...