RTL8029AS ETC-unknow, RTL8029AS Datasheet
RTL8029AS
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RTL8029AS Summary of contents
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... RTL8029AS Realtek PCI Full-Duplex Ethernet Controller with built-in SRAM ADVANCE INFORMATION REALTEK SEMI-CONDUCTOR CO., LTD. 1F, NO. 11, INDUSTRY E. RD. IX, SCIENCE-BASED INDUSTRIAL PARK, HSINCHU 30077, TAIWAN, R.O.C. TEL:886-3-5780211 FAX:886-3-5776047 3F, NO. 56, WU-KUNG 6 RD., TAIPEI HSIEN, TAIWAN, R.O.C. TEL: 886-2-2980098 FAX: 886-2-2980094, 2980097 HEAD OFFICE ...
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... CONFIG0: RTL8029AS Configuration Register 0 (03H; Type=R)..................................................................................18 CONFIG1: Reserved......................................................................................................................................................18 CONFIG2: RTL8029AS Configuration Register 2 (05H; Type=R except Bit[7:5]=R/W).................................................18 CONFIG3: RTL8029AS Configuration Register 3 (06H; Type=R except Bit[6,2:1]=R/W)..............................................19 HLTCLK: Halt Clock Register (09H; Type=W) .............................................................................................................20 8029ASID0,1: RTL8029AS ID = 8029H (0E, 0FH; Type=R) .........................................................................................20 5. PCI C ROUP ONFIGURATION 5.2.1. PCI Configuration Space Table ................................................................................................................... 20 5.2.2. PCI Configuration Space functions.............................................................................................................. 21 VID: Vendor ID Register (01-00H ...
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... SVID: Subsystem Vendor ID Register (2C-2DH; Type=R).................................................................................. 23 SID: Subsystem ID Register (2E-2FH; Type=R)................................................................................................. 24 BROMBAR: Boot ROM Base Address Register (33-30H; Type=R/W except Bit12-1=R)....................................................24 ILR: Interrupt Line Register (3CH; Type=R/W) ..................................................................................................................24 IPR: Interrupt Pin Register (3DH; Type=R).........................................................................................................................24 6. FUNCTION DESCRIPTION............................................................................................................................... 25 6.1. RTL8029AS C P ONFIGURATION 6.2. 9346 C .................................................................................................................................................. 26 ONTENTS 6.2.1 Detail values of 9346 CONFIG2-3 & ...
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... Supports 8K, 16K and 32K Boot ROM size m Use 9346 (64*16-bit EEPROM) to store resource configurations and ID parameters m Capable of programming blank 9346 on board for manufacturing convenience m Supports 4 diagnostic LED pins with programmable outputs P.S. “¯” denotes new feature of RTL8029AS LS009.0 1997.01.16 RTL8029AS Preliminary ...
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... PCI can relieve the users from pains of taking care the system resource conflict. The RTL8029AS controller also supports full-duplex and power down features. With three levels power down control features, the RTL8029AS controller is made ideal choice of the network device for a GREEN PCI PC system. The full-duplex function enables simultaneously transmission and reception on the twisted-pair link to a full-duplex Ethernet switching hub ...
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... VDD 1 CBE3B 2 IDSEL 3 AD23 4 AD22 5 AD21 6 AD20 7 AD19 8 AD18 9 AD17 10 AD16 11 GND 12 CBE2B 13 FRAMEB 14 IRDYB 15 TRDYB LS009.0 1997.01.16 RTL8029AS RTL8029AS Preliminary 65 MA11 64 MA10 63 MA9 62 MA8 61 MA7 60 MA6 59 MA5 58 MA4 57 MA3[EESK] 56 MA2[EEDI] 55 MA1[EEDO] 54 MA0 53 EECS 52 VDD 51 MA14 BOEB 48 GND 47 MD0 ...
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... CLK 92-99, 3- AD31-0 10, 20, 21, 23-28, 30- 33, 35-38 1, 12, 19, CBE3-0B 29 LS009.0 1997.01.16 RTL8029AS Preliminary Type P +5V DC power P Ground Type Descriptions I Bus Clock provides timing for all transactions on PCI and is an input pin to every PCI device. All bus signals are sampled on the rising edge of CLK and all parameters are defined with respect to this edge ...
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... Initialization Device Select is used as a chip select for RTL8029AS controller during configuration read and write transaction. I When RSTB is asserted low, the RTL8029AS performs an internal system hardware reset. RSTB must be held for a minimum of 120 ns periods. RSTB may be asynchronous to CLK when asserted or deasserted recommended that the deassertion be synchronous to guarantee clean and bounce free edge ...
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... It must be left open when X1 is driven with an external oscillator. Type O This pin goes high when RTL8029AS's medium type is set to 10Base2 mode or auto-detect mode with link test failure. Otherwise, this pin is low. This pin can be used to control the power of the DC converter for CX MAU and connected to an LED to indicate the used medium type ...
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... REGISTER DESCRIPTIONS The registers in RTL8029AS controller can be roughly divided into two groups by their address and functions -- one for NE2000, the other for PCI Configuration Space. 5.1. Group 1: NE2000 Registers This group includes 4 pages of registers which are selected by bit PS0 & PS1 in the CR register. ...
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... FB4 FB14 FB13 FB12 FB22 FB21 FB20 FB30 FB29 FB28 FB38 FB37 FB36 FB46 FB45 FB44 FB54 FB53 FB52 FB62 FB61 FB60 RTL8029AS Preliminary Bit 3 Bit 2 Bit 1 Bit 0 RD0 TXP STA STP A11 A10 A9 A8 A11 A10 A9 A8 A11 ...
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... R *0FH 8029ASID1 R Notes: The registers marked with type='W*' can be written only if bits EEM1=EEM0=1. Notes: " " denotes the bits or registers which are RTL8029AS defined bits or * registers and are not supported in RTL8029. 5.1.2. Register Functions 5.1.2.1. NE2000 Compatible Registers CR: Command Register (00H; Type=R/W) This register is used to select register pages, enable or disable remote DMA operation and issue commands ...
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... RD1 RD0 STA STP Function 1 0 Start Command 0 1 Stop Command Description RTL8029AS Preliminary Remark NE2000 compatible NE2000 compatible NE2000 compatible RTL8029AS Configuration Function Not allowed Remote Read Remote Write Send Packet Abort/Complete remote DMA 13 ...
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... LB1 LB0 Mode Conditions CRC Logic Activities Mode CRC Generator 0 normal enabled 1 normal disabled 0 loopback enabled 1 loopback disabled RTL8029AS Preliminary Remark Normal Operation Internal Loopback External Loopback External Loopback CRC Checker enabled enabled disabled enabled 14 ...
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... NIC is in monitor mode. Increment CNTR2 tally counter Always 0. 2 FAE Frame Alignment Error bit reflects the incoming packet didn't end on a byte boundary and CRC did not match at last byte boundary. Increment CNTR0 tally counter. LS009.0 1997.01.16 RTL8029AS Preliminary Description Description Description 15 ...
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... These two registers set the start address of remote DMA. RBCR0,1: Remote Byte Count Registers (0AH & 0BH; Type=W in Page0) These two registers set the data byte counts of remote DMA. CNTR0: Frame Alignment Error Tally Counter Register (0DH; Type=R in Page0) LS009.0 1997.01.16 RTL8029AS Preliminary 16 ...
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... MAR0-7: Multicast Address Register (08H - 0FH; Type=R/W in Page1) These registers provide filtering bits of multicast addresses hashed by the CRC logic. 5.1.2.2. RTL8029AS Defined Registers Page 0 (PS1=0, PS0=0) Two registers are defined to contain the RTL8029AS chip ID and Read Sequence Command is NO LONGER supported in RTL8029AS. No. Name ...
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... CONFIG0: RTL8029AS Configuration Register 0 (03H; Type=R) Bit Symbol 7-3 - Not used 2 BNC When set, this bit indicates that the RTL8029AS is using the 10Base2 thin cable as its networking medium. This bit will be set in the following 2 cases: (1) PL1=PL0=0 (auto-detect) and link test fails (2) PL1=PL0=1 (10 Base 2) 1-0 - Always 0s. CONFIG1: Reserved CONFIG2: RTL8029AS Configuration Register 2 (05H ...
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... Unused 6 FUDUP When this bit is set, RTL8029AS is set to the full-duplex mode which enables simultaneously transmission and reception on the twisted-pair link to a full- duplex Ethernet switching hub. This feature not only increases the channel bandwidth from Mbps but also avoids the performance degrading problem due to the channel contention characteristics of the Ethernet CSMA/CD protocol ...
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... HLTCLK: Halt Clock Register (09H; Type=W) This is the only active one of Group1 registers when RTL8029AS is inactivated. Writing to this register is invalid if RTL8029AS is not in power down mode. (i.e., If PWRDN bit in CONFIG3 register is zero.) The data written to this register determines the RTL8029AS's power down mode. ...
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... The Vendor ID register is a 16-bit register that identifies the manufacturer of the RTL8029AS controller. Realtek Vendor ID = 10ECH(default value) DID: Device ID Register (03-02H; Type=R) The Device ID register is a 16-bit register that shows the device ID of the RTL8029AS controller. RTL8029AS Device ID = 8029H(default value) LS009.0 1997 ...
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... Fast Back-to-Back Capable. Read as 0, write operation has no effect. 6-0 - Reserved area. Read as 0, write operation has no effect. RID: Revision ID Register (08H; Type=R) The Revision ID register is an 8-bit register that specifies the RTL8029AS controller revision number. Revision ID = 00H LS009.0 1997.01.16 RTL8029AS Preliminary ...
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... Read as 0, write operation has no effect. LTR: Latency Timer Register (0DH; Type=R) This register is an 8-bit register. LTR = 00H indicates when the RTL8029AS controller is preempted, it will release the bus immediately after finishing the current data transfer. BAR: Base Address Register (13-10H; Type=R/W except Bit4-0=R) The Base Address register is a 32-bit register that determines the I/O space mapping of the RTL8029AS controller ...
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... ILR: Interrupt Line Register (3CH; Type=R/W) The Interrupt Line register is an 8-bit register used to communicate with the routing of the interrupt written by the POST software to set interrupt line for the RTL8029AS controller. ILR = 00-0FH IPR: Interrupt Pin Register (3DH; Type=R) The Interrupt Pin register is an 8-bit register indicating the interrupt pin used by the RTL8029AS controller ...
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... BIOS software. The system BIOS has to find where the system resources are available, such as I/O base address, BROM memory base address, and interrupt request line, and assigns the resources to the required devices. At the same time the RTL8029AS controller performs a series of EEPROM read operation after power-up to set Ethernet ID, media type, operation mode ¡ ...
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... P.S. '*' denotes don't care. Note: RTL8029AS checks the 8029ASID word in 9346 when power up. If the value matches “8029h”, the RTL8029AS works in RTL8029AS mode. You can use all new features Programmable Vendor ID works like RTL8029. All enhanced functions and registers are not available. ...
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... ID PROM Contents The RTL8029AS emulates the ID PROM of NE2000 internally. After 9346 is loaded, the contents of ID PROM are as follows. offset 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H ...
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... Local Memory Bus Control The local memory bus of RTL8029AS is shared by the BROM & 9346 EEPROM.The following diagram demonstrates their connection relationship. MD7-0 MD7-0 BOEB Figure 1. Local Memory Bus Block Diagram 6.4. Flow Control The RTL8029AS supports IEEE802.3X flow control to improve performance in full-duplex mode ...
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... This section describes the lighting behaviors of the LED output signals which may be selected by LEDS1 and LEDS0 bits in the Page3 CONFIG3 register. P. assumed that the LED is on when the signal goes low. 6.5.1 LED_TX: Tx LED 6.5.2 LED_RX: Rx LED LS009.0 1997.01.16 RTL8029AS Preliminary Power On LED=low Transmitting Packet? Yes + LED=high for (100 10) ms ...
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... LED_CRS=LED_TX+LED_RX: Carrier Sense LED 6.5.4 LED_COL: Collision LED LS009.0 1997.01.16 RTL8029AS Preliminary Power On LED=low Packet? Yes + LED=high for (100 10 LED=low for ( Power On LED=high Collision (except Heartbeat)? Yes + LED=low for ( ...
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... LED_CRS 6.6. Loopback Diagnostic Operation 6.6.1. Loopback operation The RTL8029AS provides 3 loopback modes. By loopback test, we can verify the integrity of data path, CRC logic, address recognition logic and cable connection status. Mode 1: Loopback through the NIC (LB1=0, LB0=1 in TCR). The NRZ data is not transmitted to the SNI but instead it's loopbacked to the NIC's Rx deserializer ...
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... Select a loopback mode (e.g. mode 2) to test A. To test CRC generator s set RCR=00H to accept physical packet s set PAR0-5 to accept packet s set TCR=04H (CRC enabled) s set DCR=43H s clear ISR packet s check CRC bytes in FIFO after loopback B. To test CRC checker LS009.0 1997.01.16 RTL8029AS Preliminary 32 ...
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... Tx a packet s check ISR after loopback Expected: ISR=02H (packets rejected response) (4) To Test Cable Connection q There are four physical medium types in RTL8029AS. We perform loopback mode 3 to test the cable connection status. s set RCR=00H to accept physical packet s set PAR0-5 to accept packet ...
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... If MAU not connected, get TSR=51H (Carrier sense is lost during transmission and CD heartbeat fails.). C. 10BaseT with link test disabled RTL8029AS disables link test in this case, so cable OK or FAIL doesn't affect TSR; get TSR=01H. D. Auto-detection (10BaseT with link test enabled) RTL8029AS automatically switches from 10BaseT to 10Base2 if the twisted-pair wire is not connected (10BaseT link test fails). If twisted-pair wire OK, get TSR=01H (Tx OK) & ...
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... D.C. Characteristics (Tc=0 ¢ ¢J, Vcc=5V + 5%) Symbol Parameter Vil Input Low Voltage Vih Input High Voltage Vol Low-level output voltage Voh High-level output voltage II Input Leakage Current 7.3. A.C. Timing Characteristics 7.3.1. PCI Configuration Read/Write LS009.0 1997.01.16 RTL8029AS Preliminary Min. Typ. Max. 0.8 2.0 5.5 0.55 2 Unit Conditions Io=3mA, 6mA ...
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... Configuration Read CLK FRAMEB IDSEL ADDR AD31-0 CBE3-0B CMD IRDYB TRDYB DEVSELB PAR 7.3.1.2. Configuration Write CLK FRAMEB IDSEL AD31-0 ADDR CBE3-0B CMD IRDYB TRDYB DEVSELB LS009.0 1997.01.16 RTL8029AS Preliminary DATA ADDR CMD BE DATA ADDR CMD BE DATA BE DATA BE 36 ...
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... PCI I/O Read/Write 7.3.2.1. PCI I/O Read CLK FRAMEB AD31-0 ADDR CMD CBE3-0B IRDYB TRDYB DEVSELB PAR 7.3.2.2. PCI I/O Write CLK FRAMEB AD31-0 ADDR CBE3-0B CMD IRDYB TRDYB DEVSELB LS009.0 1997.01.16 RTL8029AS Preliminary DATA ADDR CMD BE DATA ADDR CMD BE DATA BE DATA BE 37 ...
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... BROM Read CLK FRAMEB AD31-0 ADDR CBE3-0B CMD IRDYB TRDYB DEVSELB PAR 7.3.4. Output Timing for PCI Interface CLK OUTPUT DELAY Tri-State OUTPUT 7.3.5. Input Timing for PCI Interface CLK INPUT LS009.0 1997.01.16 RTL8029AS Preliminary BE T_val T_on T_off T_h T_su inputs valid DATA BE 38 ...
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... EECS goes low from EESK falling edge T7 EEDO setup to EESK falling edge T8 EEDO hold from EESK falling edge LS009.0 1997.01.16 Parameter Min. 3.0 3.0 3 RTL8029AS Preliminary Min. Typ. Max D15 D14 T6 Typ. Max. Unit 3 ...
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... REALTEK Semiconductor Co., Ltd. REALTEK reserves the right to change products or specifications without notice. This document has been carefully checked and is believed to be accurate. However REALTEK Semiconductor Co., Ltd. assumes no responsibility for inaccuracies. LS009.0 1997.01.16 RTL8029AS Preliminary 40 ...
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... Millimeter 0.51 0.91 4.General appearance spec. should be based on final visual 2.85 3.10 inspection spec. 0.30 0.42 0.26 0.15 TITLE : 100L QFP ( 14x20 mm**2 ) FOOTPRINT 4.8 mm 0.80 0.65 APPROVE 1.40 1.20 2.65 CHECK 2.40 ¡Ð 0.10 ¡Ð 12¢X REALTEK SEMI-CONDUCTOR CO., LTD RTL8029AS Preliminary PACKAGE OUTLINE DRAWING LEADFRAME MATERIAL: DWG NO. REV NO. SCALE Ricardo Chen DATE SHT NO ...