CH7003B-T Chrontel, CH7003B-T Datasheet

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... PC solution using the primary display. LINE MEMORY TRUE SCALE SCALING & DEFLICKERING ENGINE SYSTEM CLOCK PLL XCLK Figure 1: Functional Block Diagram CH7003B D ESCRIPTION YUV-RGB CONVERTER NTSC/PAL TRIPLE ENCODER DAC & FILTERS TIMING & SYNC GENERATOR ...

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... CHRONTEL ESCRIPTIONS 3.1 Package Diagram D[3] 7 D[4] 8 D[5] 9 D[6] 10 DVDD 11 D[7] 12 D[8] 13 DGND] 14 D[9] 15 D[10] 16 D[11 CHRONTEL CH7003 Figure 2: 44-pin PLCC CH7003B 39 XO/FIN AVDD 36 DVDD 35 ADDR 34 DGND VDD 30 RSET 29 GND 201-0000-023 Rev. 4.2, 4/12/2002 ...

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... CHRONTEL 1 D[3] D[3] 2 D[4] D[4] 3 D[5] D[5] 4 D[6] D[6] 5 DVDD DVDD 6 D[7] D[7] 7 D[8] D[8] 8 DGND] DGND] 9 D[9] D[9] 10 D[10] D[10] 11 D[11] D[11] 201-0000-023 Rev. 4.2, 4/12/2002 CHRONTEL CH7003 Figure 3: 44-pin TQFP (1.4 mm) CH7003B 33 XO/FIN XO/FIN AVDD 31 AVDD DVDD 30 DVDD ADDR 29 ADDR DGND 28 DGND VDD 25 VDD RSET 24 RSET GND 23 GND 3 ...

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... Luminance Output Y termination resistor with short traces should be attached between Y and ground for optimum performance. In normal operating modes other than SCART, this pin outputs the luma video signal. In SCART mode, this pin outputs the red signal. CH7003B Description 201-0000-023 Rev. 4.2, 4/12/2002 ...

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... G (Green) Component Output G This pin provides the analog Green component of the digital RGB input in the RGB Pass-Through mode. B (Blue) Component Output B This pin provides the analog Blue component of the digital RGB input in the RGB Pass-Though mode. CH7003B Description 2 C Port Operation section for 5 ...

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... RGB 16-bit 5-6-5 over two bytes RGB 24-bit 8-8-8 over three bytes YCrCb (24-bit) Cb,Y0,Cr,Y1,(CCIR656 style) RGB 24 8-8-8 over two words - ‘C’ version RGB 24 8-8-8 over two words - ‘I’ version RGB 24 (32) 8-8,8X over two words 201-0000-023 Rev. 4.2, 4/12/2002 CH7003B Format Reference ...

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... Rev. 4.2, 4/12/2002 P0a P0b RGB 5-5 R1[ R1[3] R2[4] R3[4] R1[2] R2[3] R3[3] R1[1] R2[2] R3[2] R1[0] R2[1] R3[1] G1[5] R2[0] R3[0] G1[4] G2[4] G3[4] G1[3] G2[3] G3[3] G1[2] G2[2] G3[2] G1[1] G2[1] G3[1] G1[0] G2[0] G3[0] B1[4] B2[4] B3[4] B1[3] B2[3] B3[3] B1[2] B2[2] B3[2] B1[1] B2[1] B3[1] B1[0] B2[0] B3[0] CH7003B SP1 HP1 P1a P1b P2a P2b YCrCb (16-bit Y0[7] Y1[7] Y2[7] Y0[6] Y1[6] Y2[6] Y0[5] Y1[5] Y2[5] Y0[4] Y1[4] Y2[4] Y0[3] Y1[3] Y2[3] Y0[2] Y1[2] Y2[2] Y0[1] Y1[1] Y2[1] Y0[0] Y1[0] Y2[0] Cb0[7] Cr0[7] Cb2[7] Cb0[6] Cr0[6] Cb2[6] Cb0[5] Cr0[5] Cb2[5] Cb0[4] Cr0[4] Cb2[4] Cb0[3] ...

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... Y2[2] S[1] Y0[1] Y1[1] Y2[1] S[0] Y0[0] Y1[0] Y2[0] 0 Cb0[7] Cr0[7] Cb2[7] 0 Cb0[6] Cr0[6] Cb2[6] 0 Cb0[5] Cr0[5] Cb2[5] 0 Cb0[4] Cr0[4] Cb2[4] 0 Cb0[3] Cr0[3] Cb2[3] 0 Cb0[2] Cr0[2] Cb2[2] 0 Cb0[1] Cr0[1] Cb2[1] 0 Cb0[0] Cr0[0] Cb2[0] CH7003B Y3[7] Y4[7] Y5[7] Y3[6] Y4[6] Y5[6] Y3[5] Y4[5] Y5[5] Y3[4] Y4[4] Y5[4] Y3[3] Y4[3] Y5[3] Y3[2] Y4[2] Y5[2] Y3[1] Y4[1] Y5[1] Y3[0] Y4[0] Y5[0] Cr2[7] Cb4[7] Cr4[7] Cr2[6] Cb4[6] Cr4[6] Cr2[5] Cb4[5] Cr4[5] Cr2[4] Cb4[4] Cr4[4] Cr2[3] Cb4[3] ...

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... Rev. 4.2, 4/12/2002 SP2 P0a P0b 7 RGB 5-6-5 P0b P1a P1b P0a R0[4] G1[2] R1[4] G0[2] R0[3] G1[1] R1[3] G0[1] R0[2] G1[0] R1[2] G0[0] R0[1] B1[4] R1[1] B0[4] R0[0] B1[3] R1[0] B0[3] G0[5] B1[2] G1[5] B0[2] G0[4] B1[1] G1[4] B0[1] G0[3] B1[0] G1[3] B0[0] 4 12-bit RGB (12-12) P0b P1a P1b P0a R0[7] G1[3] R1[7] G0[4] R0[6] G1[2] R1[6] G0[3] R0[5] G1[1] R1[5] G0[2] R0[4] G1[0] R1[4] B0[7] R0[3] B1[7] R1[3] B0[6] R0[2] B1[6] R1[2] B0[5] R0[1] B1[5] R1[1] B0[4] R0[0] B1[4] R1[0] B0[3] G0[7] B1[3] G1[7] G0[0] G0[6] B1[2] G1[6] B0[2] G0[5] B1[1] G1[5] B0[1] G0[4] B1[0] G1[4] B0[0] CH7003B t PH2 t HP2 t t SP2 HP2 t t SP2 HP2 P1a P1b P2a P2b 8 RGB 5-5-5 P0b P1a P1b x G1[2] x R0[4] G1[1] R1[4] R0[3] G1[0] R1[3] R0[2] B1[4] R1[2] R0[1] B1[3] R1[1] R0[0] B1[2] R1[0] G0[4] B1[1] G1[4] G0[3] B1[0] G1[3] 5 12-bit RGB (12-12) P0b P1a P1b R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] G1[2] R1[5] R0[4] B1[7] R1[4] R0[3] B1[6] R1[3] G0[7] B1[7] G1[7] G0[6] B1[4] G1[6] G0[5] B1[3] G1[5] R0[2] G1[0] R1[2] R0[1] B1[2] R1[1] R0[0] B1[1] R1[0] G0[1] B1[0] G1[1] 9 ...

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... RGB (16-8) P0b P1a P1b A0[7] G1[7] A1[7] A0[6] G1[6] A1[6] A0[5] G1[5] A1[5] A0[4] G1[4] A1[4] A0[3] G1[3] A1[3] A0[2] G1[2] A1[2] A0[1] G1[1] A1[1] A0[0] G1[0] A1[0] R0[7] B1[7] R1[7] R0[6] B1[6] R1[6] R0[5] B1[5] R1[5] R0[4] B1[4] R1[4] R0[3] B1[3] R1[3] R0[2] B1[2] R1[2] R0[1] B0[1] R1[1] R0[0] B0[0] R1[0] 9 YCrCb 8-bit P0b P1a P1b P2a Y0[7] Cr0[7] Y1[7] Cb2[7] Y0[6] Cr0[6] Y1[6] Cb2[6] Y0[5] Cr0[5] Y1[5] Cb2[5] Y0[4] Cr0[4] Y1[4] Cb2[4] Y0[3] Cr0[3] Y1[3] Cb2[3] Y0[2] Cr0[2] Y1[2] Cb2[2] Y0[1] Cr0[1] Y1[1] Cb2[1] Y0[0] Cr0[0] Y1[0] Cb2[0] CH7003B P2b P3a P3b Y2[7] Cr2[7] Y3[7] Y2[6] Cr2[6] Y3[6] Y2[5] Cr2[5] Y3[5] Y2[4] Cr2[4] Y3[4] Y2[3] Cr2[3] Y3[3] Y2[2] Cr2[2] Y3[2] Y2[1] Cr2[1] Y3[1] Y2[0] Cr2[0] Y3[0] 201-0000-023 Rev. 4.2, 4/12/2002 ...

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... SAV (the synchronization reference at the start of active video SP3 P0a P0b P0b P0c P1a P1b G0[7] R0[7] B1[7] G1[7] G0[6] R0[6] B1[6] G1[6] G0[5] R0[5] B1[5] G1[5] G0[4] R0[4] B1[4] G1[4] G0[3] R0[3] B1[3] G1[3] G0[2] R0[2] B1[2] G1[2] G0[1] R0[1] B1[1] G1[1] G0[0] R0[0] B1[0] G1[0] CH7003B P2a P2b P3a Cb2[7] Y2[7] Cr2[7] Cb2[6] Y2[6] Cr2[6] Cb2[5] Y2[5] Cr2[5] Cb2[4] Y2[4] Cr2[4] Cb2[3] Y2[3] Cr2[3] Cb2[2] Y2[2] Cr2[2] Cb2[1] Y2[1] Cr2[1] Cb2[0] Y2[0] Cr2[0] t PH3 t HP3 P0c P1a P1b P1c 6 RGB 8-bit P1c P2a P2b R1[7] B2[7] ...

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... When genlocked, the CH7003 can also stop "dot crawl" motion (for composite mode operation, in NTSC modes) to eliminate the annoyance of moving borders. Both of these features are under programmable control through the register set. 12 CH7003B 201-0000-023 Rev. 4.2, 4/12/2002 ...

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... CH7003B Pixel Horizontal Vertical Clock Total Total 24.671 784 525 28.196 784 600 30.210 800 630 39.273 1040 630 43.636 1040 700 47.832 1064 750 21.147 840 420 26.434 840 525 30 ...

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... Composite Off: In Composite-off state, power is shut off to the unused DAC associated with CVBS output. Full Power Down: In this power-down state, all but the serial port circuits are disabled. This places the CH7003 in its lowest power consumption mode. 14 CH7003B 201-0000-023 Rev. 4.2, 4/12/2002 ...

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... The composite luminance and chrominance frequency response is depicted in Figure 7 through 9. 201-0000-023 Rev. 4.2, 4/12/2002 Luminance Bandwidth with Sin(X) /X (MHz) CVBS S-Video YCV YSV[1:0], YPEAK = 0.95 2.26 3.37 2.26 1.18 2.82 4.21 2.82 0.81 1.93 2.87 1.93 0.99 2.36 3.52 2.36 1.27 3.03 4.51 3.03 1.57 3.75 5.59 3.75 1.07 2.56 3.81 2.56 1.33 3.17 4.72 3.17 1.13 2.69 4.01 2.69 1.42 3.39 5.05 3.39 0.95 2.28 3.39 2.28 1.19 2.84 4.24 2.84 1.36 3.25 4.84 3.25 0.95 2.26 3.37 2.26 1.18 2.82 4.21 2.82 1.42 3.39 5.05 3.39 0.98 2.35 3.50 2.35 1.13 2.70 4.02 2.70 1.21 2.89 4.31 2.89 1.18 2.82 4.20 2.82 1.44 3.44 5.13 3.44 1.56 3.73 5.56 3.73 1.18 2.82 4.20 2.82 1.31 3.13 4.66 3.13 1.44 3.43 5.11 3.43 CH7003B S-Video YSV[1:0], YPEAK = 3.37 5.23 2.57 4.44 4.21 6.53 3.21 5.56 2.87 4.46 2.19 3.79 3.52 5.46 2.68 4.64 4.51 7.00 3.44 5.95 5.59 8.68 4.27 7.38 3.81 5.92 2.91 5.04 4.72 7.33 3.60 6.23 4.01 6.22 3.06 5.29 5.05 7.84 3.85 6.67 3.39 5.26 2.59 4.48 4.24 6.58 3.23 5.59 4.84 7.52 3.70 6.39 3.37 5.23 2.57 4.44 4.21 6.53 3.21 5.56 5.05 7.84 3.85 6.67 3.50 5.43 2.67 4.62 4.02 6.24 3.07 5.30 4.31 6.68 3.29 5.68 4.20 6.53 3.21 5.55 5.13 7.97 3.92 6.77 5.56 8.63 4.24 7.34 4.20 6.52 3.20 5.54 4.66 7.24 3.56 6.16 5.11 7.94 3.90 6.75 1X 5.23 6.53 4.46 5.46 7.00 8.68 5.92 7.33 6.22 7.84 5.26 6.58 7.52 5.23 6.53 7.84 5.43 6.24 6.68 6.53 7.97 8.63 6.52 7.24 7.94 15 ...

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... Figure 8: S-Video Luminance Frequency Response (YSV = 1X, YPEAK = n n CH7003B 201-0000-023 Rev. 4.2, 4/12/2002 ...

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... Luminance and Chrominance Filter Options (continued -12 12 -18 18 < > i UVfirdB <i> n (UVfirdB ) n -24 24 -30 30 - Figure 9: Chrominance Frequency Response 201-0000-023 Rev. 4.2, 4/12/2002 n CH7003B ...

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... Active video and black ( times vary greatly due to different scaling ratios used in different modes. 4. Black times (F and H) vary with position controls. 18 The general parameters used to Level (mV) NTSC PAL 1.49 - 1.51 287 300 4. 0.59 - 0.61 287 300 2.50 - 2.53 287 300 1.55 - 1.61 287 300 0.00 - 7.50 340 300 37.66 - 52.67 340 300 0.00 - 7.50 340 300 201-0000-023 Rev. 4.2, 4/12/2002 CH7003B Duration (uS) NTSC PAL 1.48 - 1.51 4.69 - 4.71 0.88 - 0.92 2.24 - 2.26 2.62 - 2.71 0.00 - 8.67 34.68 - 52.01 0.00 - 8.67 ...

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... CH7003B 270 271 272 273 274 275 267 267 268 268 270 ...

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... A N ALO G FIE LD 4 FIE LD 4 312 313 314 315 316 317 312 313 314 315 316 ° ° ° ° CH7003B 318 3 18 319 31 9 320 32 0 321 321 322 322 ...

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... Figure 13: NTSC Y (Luminance) Output Waveform (DACG = 0) Color/Level mA V White 26.75 1.003 Yellow 24.62 0.923 Cyan 21.11 0.792 Green 18.98 0.712 Magenta 15.62 0.586 Red 13.49 0.506 Blue 10.14 0.380 Blank/Black 8.00 0.300 Sync 0.00 0.000 Figure 14: PAL Y (Luminance) Video Output Waveform (DACG = 1) 201-0000-023 Rev. 4.2, 4/12/2002 Color bars: Color bars: CH7003B 21 ...

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... Peak Burst 19.21 0.720 Blank 15.24 0.572 Peak Burst 11.28 0.423 Yellow/Blue 6.56 0.246 Green/Magenta 3.81 0.143 Cyan/Red 2.97 0.111 Figure 16: PAL C (Chrominance) Video Output Waveform (DACG = 1) 22 Color bars: 3.579545 MHz Color Burst (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7003B 201-0000-023 Rev. 4.2, 4/12/2002 ...

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... Color/Level V Peak Chrome 33.31 1.233 White 26.75 1.003 Peak Burst 11.97 0.449 8.00 0.300 Blank/Black Peak Burst 4.04 0.151 0.00 0.000 Sync Figure 18: Composite PAL Video Output Waveform (DACG = 1) 201-0000-023 Rev. 4.2, 4/12/2002 Color bars: 3.579545 MHz Color Burst (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7003B 23 ...

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... and C, the total capacitance pF) P for the HIGH level, this input current limits the maximum value (where and I DD input P CH7003B +VDD R P DATAN2 OUT SCLK DATA IN2 IN2 SLAVE ) input ...

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... CH7003 at the register location specified by the address AR[5:0]. Register Address Byte (RAB AutoInc AR[5] 201-0000-023 Rev. 4.2, 4/12/2002 ACK Data ACK 1 CH7003 CH7003 acknowledge acknowledge AR[4] AR[3] CH7003B Alternating mode Data n ACK Stop CH7003 Condition acknowledge ADDR* ADDR R AR[2] AR[1] AR[0] 25 ...

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... Register Address Byte (RAB), is the data to be written into the register specified by AR[5:0]. If AutoInc = 0, then another RAB is expected from the master device, followed by another data byte, and so on from 1 Master Start Condition Figure 21: Acknowledge on the Bus CH7003B not acknowledge acknowledge clock pulse for acknowledgement 201-0000-023 Rev. 4.2, 4/12/2002 ...

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... RAB ACK Data ACK Figure 22: Alternating Write Cycles CH7003 acknowledge ACK RAB n ACK Data n CH7003B CH7003 CH7003 acknowledge acknowledge RAB ACK Data ACK Condition CH7003 CH7003 acknowledge acknowledge ACK ...

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... RAB 2 ACK Restart Device ID Condition Figure 24: Alternating Read Cycle CH7003 acknowledge Serial Port R/W*= ACK Restart Device ID R/W* Condition CH7003B CH7003 acknowedge Master does not acknowledge Serial Port R/W*= R/W* ACK Data 1 ACK Restart Condition Master does not acknowledge CH7003 ...

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... Controls for the PLL and memory sections 21H 3 Control of CIV value 22H - 24H 8 each Readable register containing the calculated subcarrier increment value 25H 5 Device version number 26H - 29H 30 Reserved for test (details not included herein) 2AH 6 Current register being addressed CH7003B Functional Summary 29 ...

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... FSCI11 FSCI7 FSCI3 PLLCPl PLLCAP PLLS CIV21 CIV20 CIV19 CIV13 CIV12 CIV11 CIV5 CIV4 CIV3 VID4 VID3 AR5 AR4 AR3 CH7003B Bit 2 Bit 1 Bit 0 SR2 SR1 SR0 FF1 FF0 YSV1 YSV0 YCV IDF2 IDF1 IDF0 XCM0 PCM1 PCM0 SAV2 SAV1 SAV0 ...

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... NTSC PAL-M CH7003B S ymbol: DMR Address: 00H Bits SR2 SR1 SR0 R/W R/W R Output Scaling Pixel Clock (MHz) Format PAL 5/4 21 ...

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... S-Video luma channel and two filter options in the composite luma channel. Table 20 and Table 21 show the various settings Comments Comments CBW1 CBW0 YPEAK R/W R/W R CH7003B Symbol: FFR Address: 01H Bits FF1 FF0 R/W R Symbol: VBW Address: 03H Bits YSV1 ...

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... Default: This register sets the variables required to define the incoming pixel data stream, including data format and input bit width, and VBI encoding. 201-0000-023 Rev. 4.2, 4/12/2002 RGBBP IDF3 R/W R CH7003B Symbol: IDF Address: 04H Bits IDF2 IDF1 IDF0 R/W R/W R/W ...

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... CH7003B Symbol: CM Address: 06H Bits XCM0 PCM1 PCM0 R/W R/W R 201-0000-023 Rev. 4.2, 4/12/2002 ...

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... SAV8 (bit 2) is the MSB of the start of active video value (see explanation under “Start Active Video Register”). 201-0000-023 Rev. 4.2, 4/12/2002 SAV5 SAV4 SAV3 R/W R/W R CH7003B Symbol: SAV Address: 07H Bits SAV2 SAV1 SAV0 R/W R/W R Symbol: PO Address: 08H ...

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... BL4 BL3 R/W R/W R HP5 HP4 HP3 R/W R/W R VP5 VP4 VP3 R/W R/W R CH7003B Symbol: BLR Address: 09H Bits BL2 BL1 BL0 R/W R/W R Symbol: HPR Address: 0AH Bits HP2 HP1 HP0 R/W R/W R Symbol: VPR Address: 0BH ...

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... VCO divided outputs). S-Video DACs are powered down. All circuits and pins are active. All circuitry is powered down, except serial port circuit CH7003B Symbol: SPR Address: 0DH Bits ...

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... From this point on, the video signal is pulled towards the white direction, with the effect increasing with increasing settings of CE[2:0 1.235V). If the measured voltage is below this threshold threshold CH7003B Symbol: CDR Address: 10H Bits CVBST SENSE ...

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... Normal Contrast = (17/16)*(Y -0) out in = (9/8)*(Y -0) out in = (5/4)*(Y -0) out in = (3/2)*(Y -0) = Enhances White out in 256 224 192 160 128 128 160 Reserved Reserved R/W R CH7003B 192 224 256 Symbol: MNE Address: 13H Bits R ...

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... NTSC, 5:6 106 63 19 800X600, PAL, 1 800X600, PAL, 5:6 108 61 21 800X600, PAL, 3 800X600, NTSC, 5 800X600, NTSC, 3 800X600, NTSC, 7:10 190 89 CH7003B Symbol: PLLM Address: 14H Bits R/W R/W R Symbol: PLLN Address: 15H Bits R/W R/W ...

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... TV vertical sync (for test use only) Table 28. K3 Selection SHF[2:0] K3 000 2.5 001 3 010 3.5 011 4 100 4.5 101 5 110 6 111 7 201-0000-023 Rev. 4.2, 4/12/2002 SHF2 SHF1 SHF0 R/W R/W R Buffered Clock Output CH7003B Symbol: BCO Address: 17H Bits SCO2 SCO1 SCO0 R/W R/W R ...

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... FSCI# R/W NTSC "No Dot Crawl" 763,366,524 623,156,346 574,432,187 463,964,459 646,236,211 516,988,968 452,365,347 623,156,346 545,261,803 508,911,016 521,960,016 469,764,015 438,556,645 CH7003B Symbol: FSCI Address: 018H - 1FH Bits: 4 each FSCI# FSCI# FSCI# R/W R/W R/W PAL-M "Normal Dot Crawl 762,524,467 622,468,953 573,798,541 463,452,668 645,523,358 516,418,687 ...

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... PLLCHI controls the charge pump current of the PLL. The default value of 0 should be used. 201-0000-023 Rev. 4.2, 4/12/2002 PAL-N "Normal Dot Crawl" 651,209,077 520,967,262 486,236,111 392,125,896 547,015,625 434,139,385 651,209,077 520,967,262 434,139,385 521,519,134 427,355,957 394,482,422 PLLCPI PLLCAP PLLS R/W R/W R CH7003B Symbol: PLLC Address: 20H Bits PLL5VD PLL5VA MEM5V R/W R/W R ...

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... CHRONTEL Table 31. PLL Capacitor Setting Mode PLLCAP Value CH7003B 201-0000-023 Rev. 4.2, 4/12/2002 ...

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... Rev. 4.2, 4/12/2002 CIV# CIV# CIV N/A VID4 VID3 CH7003B Symbol: CIVC Address: 21H Bits CIVH1 CIVH0 ACIV R/W R/W R Symbol: CIV Address: 22H - 24H Bits: 8 each CIV# CIV# CIV ...

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... The Address Register points to the register currently being accessed. Since the most significant four bits of all addresses are zero, this register contains only the six least significant bits, AR[5:0 AR5 AR4 AR3 R/W R/W R CH7003B Symbol: AR Address: 2AH Bits AR2 AR1 AR0 R/W R/W R 201-0000-023 Rev ...

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... S-Video & composite outputs) DVDD (3.3V) current RSET = 360 , VREF = 1.235V, and NTSC CCIR601 operation. 201-0000-023 Rev. 4.2, 4/12/2002 Min - 0.5 1 GND - 0 Min 4.75 4.75 3 Min Typ 9 9 33.89 105 40 CH7003B Typ Max Units 7.0 V VDD + 0.5 V Indefinite Sec 125 C 150 C 150 C 220 C It should be handled as an Typ Max Units 5.00 5 ...

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... High Voltage V P-OUT Output P-OUTOL Low Voltage Note refers to all digital pixel and clock inputs. DATA V - refers to pixel data output Time - Graphics. P-OUT 48 Test Condition IOL = 2.0 mA GND-0.5 Vref+0.25 GND-0.5 IOL = - 400 A IOL = 3.2 mA CH7003B Min Typ Max Unit 0.4 V 2.7 VDD + 0.5 V 1.4 V DVDD+0.5 V Vref-0.25 V 2.8 V 0.2 V ...

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... Differential Clock: (XCLK = XCLK*) to (D[11:0 & VREF) Single-ended Clock: (XCLK =VREF) to (D[11:0 & VREF) t5 D[11:0 & DS rise/fall time w/15pF load 201-0000-023 Rev. 4.2, 4/12/2002 PIXELS 1 VGA Line t5 t5 Parameter CH7003B P0a P0b P1a P1b P2a t3 Min Typ Max 1 ...

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... Single-ended Clock: (XCLK =VREF) to (D[11:0 & VREF) t5 D[11:0 & DS rise/fall time w/15pF load Hold time: t6 P-OUT to HSYNC, VSYNC delay t7 (P-OUT=VREF) to (XCLK =XCLK*) delay PIXELS 1 VGA Line Parameter CH7003B P0a P0b P1a P1b P2a t3 Min Typ Max 1.7 3.6 DVDD2 - 0.2 DVDD2 + 0 ...

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... VIEW A B Table of Dimensions (inches, unless specified) No. of Leads mm) 0.685 MIN Milli- meters 0.695 MAX 201-0000-023 Rev. 4.2, 4/12/2002 SYMBOL 0.650 0.020 0.050 0.656 – CH7003B BOTTOM VIEW 0.013 0.590 0.165 0.021 0.630 0.180 51 ...

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... mm) MIN 11.80 9.90 Milli- meters MAX 12.20 10.10 MIN 0.465 0.390 Inches MAX 0.480 0.398 SYMBOL 0.30 1.35 0.05 0.80 0.40 1.45 0.15 0.012 0.0531 0.00197 0.031 0.016 0.0571 0.0059 CH7003B LEAD E .004 0.50 0 1.016 0.75 0.17 7 0.0197 0 0.040 0.0295 0.0067 7 201-0000-023 Rev. 4.2, 4/12/2002 ...

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... CHRONTEL Part number CH7003B-V CH7003B-T 2002 Chrontel, Inc. All Rights Reserved. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death ...