CH7315B-TEF Chrontel, CH7315B-TEF Datasheet
CH7315B-TEF
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CH7315B-TEF Summary of contents
Page 1
... RGB, 4:2:2 YCbCr or 4:4:4 YcbCr data. The CH7315B device also supports up to 8-channel audio output at 192 KHz. audio data. Available audio bandwidth depends on the pixel clock frequency, the video format timing, and whether or not content protection re-synchronization is needed ...
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... A/V buffers Figure 1: Functional Block Diagram 201-0000-079 CH7315B 2 SDVOB_ INT(+,-) Interrupt Generation HPDET1 HPDET2 2 TLAC (+,-) HDMI 2 TDAC 0 (+,-) Output 2 (+,-) TDAC 1 Switch 2 TDAC 2 (+,-) 2 TLBC (+,-) 2 TDBC 0 (+,-) 2 TDBC 1 (+,-) 2 TDBC 2 ...
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... HDCP Compatibility ________________________________________________________________9 2.5 HDMI Transmitter _________________________________________________________________10 2.6 Command Interface ________________________________________________________________12 3.0 Register Control ____________________________________________________________ 13 4.0 Electrical Specifications ______________________________________________________ 14 4.1 Absolute Maximum Ratings __________________________________________________________14 4.2 Recommended Operating Conditions ___________________________________________________14 4.3 Electrical Characteristics ____________________________________________________________15 4.4 DC Specifications __________________________________________________________________15 4.5 AC Specifications __________________________________________________________________18 5.0 Package Dimensions _________________________________________________________ 20 6.0 Revision History ____________________________________________________________ 21 201-0000-079 Rev. 1.4, 1/7/2008 Table of Contents CH7315B 3 ...
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... BCLK 3 AGND_PLL SC_PROM 4 SD_PROM 5 AVDD_PLL 6 7 SC_DDC0 8 SD_DDC0 9 SPC 10 SPD DGND 11 SC_DDC1 12 SD_DDC1 13 DVDD 14 15 RESET* 16 VSWING 4 Figure 2: 64-Pin LQFP Pin Out 201-0000-079 CH7315B 48 AVDD_INT 47 SDVO_INT- 46 SDVO_INT+ 45 AGND_INT 44 S/PDIF 43 DVDD PROM2 40 PROM1 39 HPDET1 38 HPDET0 DGND 37 36 TDBC2 35 TDAC2 34 TDAC2* 33 TDBC2* Rev ...
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... HDMI Port A Data Channel 1 Outputs These pins provide the HDMI port A differential outputs for data channel 1 (green). HDMI Port A Data Channel 2 Outputs These pins provide the HDMI port A differential outputs for data channel 2 (red). HDMI Port B Clock Outputs CH7315B unused. 2.5V. 2.5V. unused. outputs. 5 ...
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... SDO with respect to every edge of BCLK. SYNC signal for audio side This signal marks input and output frame boundaries (Frame Sync) as well as identifying outbound data streams (stream tags). SYNC is always sourced from the controller. Digital Supply Voltage (2.5V) Digital Ground 201-0000-079 CH7315B Rev. 1.4, 1/7/2007 ...
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... AGND_PLL 6 Power AVDD_PLL 62 Power VDDIO 201-0000-079 Rev. 1.4, 1/7/2008 Description HDMI Transmitter Supply Voltage HDMI Transmitter Ground Interrupt block Ground Interrupt block Supply Voltage (2.5V) Analog Supply Voltage (2.5V) Analog Ground HDMI PLL Ground HDMI PLL Supply Voltage (3.3V) HDMI audio interface supply voltage (1.5V/3.3V) CH7315B (3.3V) 7 ...
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... The CH7315B synchronizes during the initialization period and subsequently uses the blank periods to re-synch to the data stream. 2.2 Audio The CH7315B can support both HD Audio and S/PDIF audio inputs. It also has the ability to decode a third party HD Audio Codec’s digital audio stream from the HD Audio Link 2.2.1 HD Audio General Description ...
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... Power Saving CH7315B offers two power saving features that allow for a significant reduction in the power consumed for the PC system normal system Power-off/Suspend procedure has taken place or GMCH has failed to communicate to TV monitor through DDC lines, the Intel Software Graphic Driver will send an Opcode* Command to CH7315B to enter Power-Down mode ...
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... These data items are processed in a variety of ways and are presented to the HDMI encoder as either 2 bits of control data, 4 bits of packet data or 8 bits of video data per HDMI channel. CH7315B encodes one of these data types or encodes a Guard Band character on any given clock cycle. ...
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... Table 4: DVI Output Formats CH7315B supports Graphics Active Aspect Resolution Ratio 720x400 4:3 640x400 8:5 640x480 4:3 800x600 4:3 1024x768 4:3 1280x720 16:9 1280x768 15:9 1280x1024 4:3 1366x768 16:9 1360x1024 ...
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... Upon reset, the default state of the directional switch is to redirect the control bus to PROM. At this stage, the CH7315B observes the control bus traffic. If the observing logic sees a control bus transaction destined for the internal registers (device address 70h or 71h based on AS pin external setting), it disables the PROM output pairs, and switches to internal registers ...
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... EGISTER ONTROL The CH7315B is controlled via a serial control port. The serial bus uses only the SC clock to latch data into registers, and does not use any internally generated clocks so that the device can be written into even in all power down modes. The device will retain all register values during power down modes. ...
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... Analog interrupt Power Supply Voltage AVDD_PLL Analog PLL Power Supply Voltage DVDD Digital Power Supply Voltage TVDD DVI Power Supply VDDIO Audio interface Power Supply voltage VDD33 Generic for all 3.3V supplies VDD25 Generic for all 2.5V supplies 14 CH7315B Min Typ Max -0.5 3.0 -0.5 5.0 Indefinite 0 85 -65 150 150 ...
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... Min Typ 0.175 RX-DIFFp-p ⏐ V ⏐ RX-D+ RX-D- 80 100 40 Impedance allowed 5 when receiver terminations are first turned 2.0 GND-0.5 0.25 4.0 GND-0.5 4.0 GND-0.5 CH7315B Typ Max Unit 210 100 uA Max Unit 1.200 V Ω 120 Ω Ω 1.2 V 0.4 V VDD25 + 0 0.4 V VDD5 + 0 ...
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... IN 10 GND-0.5 0.65*VDDI 1500 uA OUT GND-0 -500 uA OUT 0.9*VDDIO TVDD = 3.3V ± 5% TVDD – = 50Ω ± 0.01 TERM = 1200Ω ± TVDD – 0.6 SWING 400 TVDD – 0.01 201-0000-079 CH7315B Max Unit 0.9*V + 0.25 V INL 0.933*V + 0.35 V INL 0.933*V + 0.35 V INL VDD33 + 0.5 V 0.5 V VDD25 + 0.5 V 0.5 V 3.72 V 0.5 V ...
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... V refers to AS 2.5V compliant. MISC2 8. V refers to SDI, SDO, AUDSYNC, AUDRST* and BCLK which are 1.5V and 3.3V compliant. Only SDI can be output. AUD VDDIO is the audio interface supply voltage, it can be 1.5V or 3.3V. 201-0000-079 Rev. 1.4, 1/7/2008 CH7315B . Maximum output INL . Maximum INL . INL 17 ...
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... XCLK f = 165MHz XCLK f = 165MHz XCLK f = 165MHz XCLK 1 0.5 Vout=0.9VCC with -500 VDDIO=3.3V Vout=0.1VCC with 1500 VDDIO=3.3V Vout=0.9VCC with -500 VDDIO=1.5V 201-0000-079 CH7315B Typ Max Unit Typ 300ppm 200 MHz 165 MHz 2 GHz UI 0.3 UI 150 242 ps 242 ...
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... T_su Setup for ADUIO Input SDO at both rising and falling edge of BCLK T_h Hold for SDO at both rising and falling edge of BCLK 201-0000-079 Rev. 1.4, 1/7/2008 Test Condition Min Vout=0.1VCC with 1500 VDDIO=1. CH7315B Typ Max Unit ...
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... Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. 3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side .008" SYMBOL 0.17 1.35 0.05 0.50 0.27 1.45 0.15 201-0000-079 CH7315B BOTTOM VIEW K K EXPOSED PAD 0.45 0.09 0° 5.85 1.00 0.75 0.20 7° 7 Rev. 1.4, 1/7/2007 ...
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... ISTORY Table 11: Revisions Rev. # Date Section 1.0 3/14/07 All 1.1 3/16/07 1.0 1.2 8/2/07 4.4 1.3 9/7/07 1.2 & 4.4 1.4 1/7/08 1.1 & 1.2 201-0000-079 Rev. 1.4, 1/7/2008 Description Initial release General Description update. Change HPDET0, HPDET1 input high voltage spec. Update Pin 9, Pin 10, Pin 12 and Pin 13 in Table 1 and Table 9. Update Pin 44, Figure 1 and Figure 2. CH7315B 21 ...
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... SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. Part Number CH7315B-TEF CH7315B-TEF-TR ©2008 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A. 22 Disclaimer ...