QT60240 Quantum Research Group, QT60240 Datasheet
![no-image](/images/no-image-200.jpg)
QT60240
Available stocks
Related parts for QT60240
QT60240 Summary of contents
Page 1
... Printed Circuit Board (PCB) or Flexible Printed Circuit Board (FPCB copper pattern printed conductive ink on plastic film GLANCE Number of keys (QT60160 (QT60240) Technology: Patented spread-spectrum charge-transfer (transverse mode) Key outline sizes: 6mm x 6mm or larger (panel thickness dependent); widely different sizes and shapes possible ...
Page 2
... QT60240-ISG R8.06/0906 ...
Page 3
... Part Differences There are two versions of the device; one is capable of a maximum of 16 keys (QT60160), the other is capable of a maximum of 24 keys (QT60240). These devices are identical in all respects, except for the maximum number of keys specified. The keys can be located anywhere within an electrical grid and 3 Y scan lines. ...
Page 4
... Rs. However, long adjacent runs of X and Y lines can also artificially boost the signal values, and induce signal saturation; this avoided. The X-to-Y coupling should come mostly from intra-key electrode coupling, not from stray X-to-Y trace coupling. 4 QT60240-ISG R8.06/0906 ...
Page 5
... X line(s) should be reduced (by a layout change, for example by reducing X line exposure to nearby ground planes or traces), or, the Rx resistor needs to be reduced in value (or a combination of both approaches QT60240-ISG R8.06/0906 ...
Page 6
... Caution: A regulator IC shared with other logic can result in erratic operation and is not advised. A regulator can be shared among two or more QT devices on one board. One such regulator known to work well with QT chips is the S-817 series from Seiko Instruments (Seiko Instruments - www.sii-ic.com). 6 QT60240-ISG R8.06/0906 ...
Page 7
... Key touch activity will prevent the part from sleeping. The part will not sleep if any touch events were detected at any key in the most recent scan of the key matrix. 7 QT60240-ISG R8.06/0906 ...
Page 8
... If Unused, Connect To... Vdd Leave open - - - - Leave open Leave open Leave open - Leave open Leave open Leave open Leave open Leave open Leave open Leave open - - - - - Leave open Leave open Leave open - - - Leave open or Vdd Leave open Leave open Leave open QT60240-ISG R8.06/0906 ...
Page 9
... RF susceptibility improvement **RY0 CS0 4.7nF **RY1 CS1 4.7nF **RY2 CS2 4.7nF Note: Leave YnA, YnB unconnected if not used RS2 RS1 RS0 QT60240-ISG R8.06/0906 *RX4 1K *RX0 ...
Page 10
... The QT60160/QT60240 allows multiple byte transmissions to provide a more efficient communication. This is particularly useful to retrieve several information bytes at once. Every time the host retrieves data from the QT60160/QT60240, an internal address pointer is incremented. Legend Units Therefore, the host only needs to write the initial address ...
Page 11
... The configuration is set in the Setups block (Section 6.13 key-by-key basis. Figure 3.2 Shift Register Cycle Key 2 Key 21 Key 22 Key 23 Key 0 Key 3 Key 4 t SCL SCH SDA-SCL QT60240-ISG R8.06/0906 Key 23 t LATCH ...
Page 12
... Start condition SLA+W Slave address plus write bit A Acknowledge bit Target memory address within MemAddress device Data Data from device P Stop condition SLA+R Slave address plus read bit Not Acknowledge bit/indicates /A last byte transmission QT60240-ISG R8.06/0906 Device to Host SLA+R A Data ...
Page 13
... Addresses 131 to 252 provide read/write access to the setups. Details of different setups can be found in Section 6, page 17. When the host is writing a new setup block the values are being recorded into EEPROM as they arrive from the host communication sequence. Reading this QT60240-ISG R8.06/0906 ...
Page 14
... Block Incorrect Setup Data Correct Setup Block 'CHANGE' output set Host main Process Keys OK Recalibrate All Send 0x55 to Addr 125 Stuck Key Detected 14 Recalibrate All Send Correct Send 0x55 to Setup Block Addr 125 Legend Internal Host Processes Comms with QT QT60240-ISG R8.06/0906 ...
Page 15
... SDA line low during the ninth SCL cycle. If the Data Stable Receiver leaves the SDA line high, a NACK is signaled. 15 Figure 5.3 START and STOP Conditions SDA SCL START Figure 5.4 Address Packet Format Addr MSB Addr LSB START QT60240-ISG R8.06/0906 STOP R/W ACK 8 9 ...
Page 16
... SLA +R/W and the STOP. Figure 5.5 Data Packet Format Data MSB 1 2 Data Byte Figure 5.6 Packet Transmission Addr LSB R/W ACK Data MSB Data LSB ACK STOP, or Next Data Byte Data LSB ACK Data Byte QT60240-ISG R8.06/0906 9 STOP ...
Page 17
... The drift compensation mechanism can be asymmetric; the drift-compensation can be made to occur in one direction faster than it does in the other simply by changing the NDRIFT and PDRIFT Setup parameters. This can be done on a per-key basis. Figure 6.1 Thresholds and Drift Compensation Hysteresis Threshold Output 17 Reference Signal QT60240-ISG R8.06/0906 ...
Page 18
... This condition can occur if there is positive drift but insufficient positive drift compensation , or, if the reference moved negative due to a NRD auto-recalibration, and thereafter the signal rapidly returned to normal (positive excursion). 18 QT60240-ISG R8.06/0906 ( seconds) 20 (10 seconds) 0..254 (∞ ...
Page 19
... The sync signal drive should be a buffered logic signal, or perhaps a diode-clamped signal, but never a raw AC signal from the mains. The device will synchronize to the falling edge. 19 QT60240-ISG R8.06/0906 0 (Off) 0 (Off) ...
Page 20
... DHT can be configured to a value of between 100ms and 25.5s, in increments of 100ms. Setting this parameter to 0 will disable this feature and the drift compensation on any key will not be dependent on the state of other keys. DHT default value: 10 (1s) DHT range: 0...255 (Off, 100ms...25.5s) 20 QT60240-ISG R8.06/0906 25 (2.5s) 1...255 (100ms...25.5s) ...
Page 21
... MSYNC = 0 Bits 6 = Mains sync, negative edge enabled, default = off 1...255 Range is in 100ms increments 100ms. Default = 2.5s illegal to use 0...255 Range is in 100ms increments disable 100ms, default = 1s 21 Description Page QT60240-ISG R8.06/0906 ...
Page 22
... BL SLEEP AKS SSYNC MSYNC ms (Page 19) (Page 19) (Page 20) (Page 19) Per key Per key Global Global 16 - Off - - Off - -125- 250 500 1,000 2,000 QT60240-ISG R8.06/0906 AWAKE DHT secs secs (Page 20) (Page 20) Global Global - Off - unused Off On 0.1...25.5s 0.1...25.5s Default= Default= 2.5s 1s ...
Page 23
... Min Typ Max 270 380 490 600 155 ± + +125 Units Notes Vdd = 1.8V mA Vdd = 3.3V Vdd = 5.0V Vdd = 1.8V µA Vdd = 3.3V Vdd = 5.0V V 1.8V <Vdd <5V V 1.8V <Vdd < µA bits k✡ Units Notes µ kHz % QT60240-ISG R8.06/0906 ...
Page 24
... QT60240-ISG R8.06/0906 x KE) BS ...
Page 25
... 0.18 E 0.30 F 2.95 G 2.95 e 7.7 Marking MLF Part Number QT60160-ISG QT60240-ISG 7.8 Moisture Sensitivity Level (MSL) MSL Rating MSL3 Nominal Maximum 0.90 1.00 0.02 0.05 0.65 1.00 0.20 REF 5.00 BSC 5.00 BSC 0.23 0. 0.40 0.50 3.10 3.25 3.10 3.25 0.50 BSC Keys Marking 16 6160 24 6240 Peak Body Temperature Specifications O 260 C IPC/JEDEC J-STD-020C QT60240-ISG R8.06/0906 e A3 ...
Page 26
This device is covered under one or more United States and corresponding international patents. QRG patent numbers can be found online at www.qprox.com. Numerous further patents are pending, which may apply to this device or the applications thereof. The ...