QL6325-6PS484C QULOG, QL6325-6PS484C Datasheet
QL6325-6PS484C
Related parts for QL6325-6PS484C
QL6325-6PS484C Summary of contents
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... QL6325 Eclipse Data Sheet • • • • • • Combining Performance, Density, and Embedded RAM Device Highlights Flexible Programmable Logic .25 m, Five layer metal CMOS Process • 2 2.5 V/3.3 V Drive Capable I/O • CC 1,536 Logic Cells • 320,640 Max System Gates • ...
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... QL6325 Eclipse Data Sheet Rev C Electrical Specifications AC Characteristics at V The AC Specifications are provided from waveforms are provided from Symbol Logic Cells Combinatorial Delay of the longest path: time taken by the combinatorial circuit output Setup time: time the synchronous input of the flip flop must be stable before the ...
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... Figure 5: Logic Cell Flip Flop Timings - Second Waveform © 2002 QuickLogic Corporation SET D CLK RESET Figure 3: Logic Cell Flip Flop t (min) t CWHI CWLO t RESET t SET QL6325 Eclipse Data Sheet Rev C Q (min) www.quicklogic.com • • • 3 • • • ...
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... QL6325 Eclipse Data Sheet Rev C Clock Logic Cells (Internal) I/O’s (External) Clock Segment t PGCK t BGCK Programmable Clock External Clock • • • www.quicklogic.com 4 • • • Figure 6: Eclipse Global Clock Structure Table 2: Eclipse Clock Performance Parameters Clock signal generated internally Clock signal generated externally ...
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... WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the t WCRD time when the data is available at RD © 2002 QuickLogic Corporation [9:0] WA [17:0] RCLK WCLK ASYNCRD RAM Module Figure 8: RAM Module Table 4: RAM Cell Synchronous Write Timing Parameter QL6325 Eclipse Data Sheet Rev C RE [9:0] [17:0] RD Value (ns) Min 0.675 0 0.654 0 0.623 0 - www.quicklogic.com Max - - ...
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... QL6325 Eclipse Data Sheet Rev C WCLK Symbol RAM Cell Synchronous Read Timing RA setup time to RCLK: time the READ ADDRESS must be stable before the active t SRA edge of the READ CLOCK RA hold time to RCLK: time the READ ADDRESS must be stable after the active ...
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... QuickLogic Corporation t t SRA HRA t t SRE HRE old data t RCRD r PDRD INPUT REGISTER R Q OUTPUT D REGISTER REGISTER R Figure 11: Eclipse Cell I/O QL6325 Eclipse Data Sheet Rev C new data + - PAD www.quicklogic.com • • • 7 • • • ...
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... QL6325 Eclipse Data Sheet Rev C Symbol Input Register Cell Only Input register setup time: time the synchronous input of the flip-flop must be stable t ISU before the active clock edge Input register hold time: time the synchronous input of the flip-flop must be stable t IHL ...
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... E © 2002 QuickLogic Corporation Table 7: Standard Input Delays Parameter To get the total input delay add this delay to tISU t t IHL ISU t ICO t t IESU IEH Figure 13: Eclipse Input Register Cell Timing QL6325 Eclipse Data Sheet Rev C Value (ns) Min Max - 0.34 - 0.42 - 0.68 - 0.55 - 0.61 t IRST www.quicklogic.com • ...
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... QL6325 Eclipse Data Sheet Rev C Symbol Output Register Cell Only t Output Delay low to high (90 OUTLH t Output Delay high to low (10 OUTHL t Output Delay tri-state to high (90 PZH t Output Delay tri-state to low (10 PZL t Output Delay high to tri-State PHZ t Output Delay low to tri-State ...
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... Z t PZH PLZ Figure 15: Eclipse Output Register Cell Timing Table 9: Output Slew Rates @ V CCIO Fast Slew 2.8 V/ns 2.86 V/ns Table 10: Output Slew Rates @ V Fast Slew 1.7 V/ns 1.9 V/ns QL6325 Eclipse Data Sheet Rev C t OUTHL t PZL t PHZ = 3.3 V Slow Slew 1.0 V/ns 1.0 V/ns = 2.5 V CCIO Slow Slew 0.6 V/ns 0.6 V/ns www.quicklogic.com • • ...
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... QL6325 Eclipse Data Sheet Rev C DC Characteristics The DC Specifications are provided in Parameter V Voltage CC V Voltage CCIO INREF Voltage Input Voltage Latch-up Immunity Symbol V Supply Voltage CC V I/O Input Tolerance Voltage CCIO TA Ambient Temperature TC Case Temperature K Delay Factor Symbol I/O Input Leakage Current ...
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... VccI/0 = 3.0V -80 VccI/O = 3.3V -100 VccI/O = 3.6V -120 © 2002 QuickLogic Corporation IOL vs VOL 0.60 0.80 1.00 1.20 1.40 1.60 1.80 Supply voltage (V) Figure 16: IOL vs. VOL IOH vs VOH Supply voltage (V) Figure 17: IOH vs. VOH QL6325 Eclipse Data Sheet Rev C Vccio = 3.6V Vccio = 3.3V Vccio = 3.0V Vccio = 2.7V Vccio = 2.5V Vccio = 2.3V 2.00 2.20 2.40 2.60 2.80 3.00 www.quicklogic.com • • • 13 • • • ...
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... QL6325 Eclipse Data Sheet Rev C INREF MIN MAX LVTTL n/a n/a -0.3 LVCMOS2 n/a n/a -0.3 GTL+ 0.88 1.12 -0.3 PCI n/a n/a -0.3 SSTL2 1.15 1.35 -0.3 SSTL3 1.3 1.7 -0.3 NOTE: The data provided in either meet or exceed these requirements. See preceding Figure 1 NOTE: All CLK and INREF pins are clamped to the V can only be driven • ...
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... AMAX 150º calculate the maximum power JMAX JA )/ AMAX JA Table 15: Package Thermal Characteristics (º C/W) @ various flow rates (m/sec 0.5 PBGA 20.0 19.0 PBGA 28.0 26.0 18.5 17.0 PQFP 26.0 24.5 QL6325 Eclipse Data Sheet Rev C from 15, pick an appropriate T Table (º C/ 17.5 16.0 7.0 25.0 23.0 9.0 15.5 14.0 7.0 23.0 22.0 11.0 www.quicklogic.com and AMAX • • • ...
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... QL6325 Eclipse Data Sheet Rev C Kv and Kt Graphs 1.15 1.10 1.05 1.00 0.95 0.90 0.85 • • • www.quicklogic.com 16 • • • Voltage Factor vs. Supply Voltage 1.1000 1.0800 1.0600 1.0400 1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 2.25 2.3 2.35 2.4 2.45 2.5 Supply Voltage (V) Figure 18: Voltage Factor vs. Supply Voltage Temperature Factor vs. Operating Temperature -60 -40 ...
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... RAM = # of PLLs • PLL is the number of input pins • INP is the number of output pins • OUTP exhibits the power consumption in an Eclipse QL6325 device. The chip was filled Figure 20 with (300) 8-bit counters 2.5 2 1 illustrates the theoretical worst-case scenarios for 50%, 70%, and 90% utilizations Figure 21 of the 6600-516 package. The resources of the device are divided exactly in half ...
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... QL6325 Eclipse Data Sheet Rev Figure 21: Power vs. Frequency (Absolute 50%, 70%, and 90% of the Available Resources on Chip) To learn more about power consumption, please refer to application note #60 which is located at • • • www.quicklogic.com 18 • • • Power vs. Frequency ...
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... V CC 400 us Figure 22: Power-up Requirements when ramping the device. CC before reaching 400 µs can cause the device to behave improperly. and shown in CC CCIO V CC QL6325 Eclipse Data Sheet Rev C Figure 500 mV. Deviation from CCIO CC MAX . Ramping Figure 23 V CCIO ...
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... QL6325 Eclipse Data Sheet Rev C JTAG TCK TMS TRSTB RDI Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, not in the least of which concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard 1149 ...
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... QuickLogic Corporation The Extest instruction performs a PCB interconnect test. This test This instruction allows a device to remain in its The Bypass instruction allows data to skip a device's boundary QL6325 Eclipse Data Sheet Rev C www.quicklogic.com • • • ...
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... QL6325 Eclipse Data Sheet Rev C Pin Descriptions Pin Test Data In for JTAG/RAM TDI/RSI init. Serial Data In Active low Reset for TRSTB/RRO JTAG/RAM init. reset out TMS Test Mode Select for JTAG TCK Test Clock for JTAG Test data out for JTAG/RAM TDO/RCO init ...
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... This pin can also double as a high-drive pin to the internal logic cells. The A inside the parenthesis means that IOCTRL is located in Bank A. This pin should be tied to GND not used. CC QL6325 Eclipse Data Sheet Rev C level CCIO . CC www.quicklogic.com • ...
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... QL6325 Eclipse Data Sheet Rev C Recommended Unused Pin Terminations for the Eclipse devices All unused, general purpose I/O pins can be tied to V internally using the Configuration Editor. This option is given in the bottom-right corner of the placement window. To use the Placement Editor, choose Constraint in the Option pull-down menu of SpDE ...
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... PQFP Pinout Diagram © 2002 QuickLogic Corporation Eclipse QL6325-4PQ208C QL6325 Eclipse Data Sheet Rev C www.quicklogic.com • • • 25 • • • ...
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... QL6325 Eclipse Data Sheet Rev C 208 PQFP Pinout Table 208 PQFP Function 1 PLLRST( CCPLL 3 GND 4 GND 5 IO(A) 6 IO(A) 7 IO( CCIO 9 IO(A) 10 IO(A) 11 IOCTRL( INREF(A) 14 IOCTRL(A) 15 IO(A) 16 IO(A) 17 IO(A) 18 IO( CCIO 20 IO(A) 21 GND 22 IO(A) 23 TDI 24 CLK(0) 25 CLK( CLK(2),PLLIN(2) 28 CLK(3),PLLIN(1) ...
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... PBGA Pinout Diagram Top QL6325-4PT280C Bottom © 2002 QuickLogic Corporation Eclipse QL6325 Eclipse Data Sheet Rev C Pin A1 Corner www.quicklogic.com • • • 27 • • • ...
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... QL6325 Eclipse Data Sheet Rev C 280 PBGA Pinout Table 280 PBGA Function 280 PBGA Function 280 PBGA Function 280 PBGA Function 280 PBGA Function 280 PBGA A1 C10 PLLOUT<3> A2 C11 GNDPLL<0> A3 I/O<F> C12 A4 C13 I/O<F> A5 C14 I/O<F> A6 C15 IOCTRL<F> A7 C16 I/O<F> A8 C17 I/O<F> A9 C18 I/O<F> A10 C19 CLK<7> ...
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... PBGA Packaging Drawing © 2002 QuickLogic Corporation Figure 27: 280 PBGA Packaging Drawing QL6325 Eclipse Data Sheet Rev C www.quicklogic.com • • • 29 • • • ...
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... QL6325 Eclipse Data Sheet Rev C 484 PBGA Pinout Diagram Top QL6325-4PS484C Bottom • • • www.quicklogic.com 30 • • • Eclipse ...
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... GND F16 H16 V <G> I/O<F> CCIO F17 N/C H17 I/O<F> F18 H18 I/O<F> I/O<F> F19 H19 <0> I/O<F> I/O<F> F20 H20 IOCTRL<F> I/O<F> F21 H21 I/O<F> I/O<F> F22 IOCTRL<F> H22 I/O<F> (Sheet QL6325 Eclipse Data Sheet Rev I/O<A> DEDCLK/PLLIN<0> I/O<A> I/O<A> CLK<2>/PLLIN<2> I/O<A> I/O<A> I/O<A> I/O<A> GND J10 L10 ...
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... QL6325 Eclipse Data Sheet Rev C 484 PBGA Function 484 PBGA Function 484 PBGA Function 484 PBGA Function 484 PBGA Function 484 PBGA N1 P16 I/O<B> N2 P17 I/O<B> N3 P18 I/O<B> N4 P19 I/O<B> N5 P20 I/O<B> N6 P21 I/O<B> N7 P22 I/O<B> N10 R3 GND N11 R4 GND N12 GND R5 N13 R6 GND ...
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... PBGA Packaging Drawing © 2002 QuickLogic Corporation Figure 28: 484 PBGA Packaging Drawing QL6325 Eclipse Data Sheet Rev C www.quicklogic.com • • • 33 • • • ...
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... QL6325 Eclipse Data Sheet Rev C 516 PBGA Pinout Diagram Top QL6325-4PB516C Bottom • • • www.quicklogic.com 34 • • • Eclipse PIN A1 CORNER © 2002 QuickLogic Corporation ...
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... F20 V <E> K24 N/C CCIO F21 K25 GND I/O<D> F22 K26 N/C I/O<D> F23 L1 N/C I/O<G> F24 L2 I/O<D> N/C F25 N/C L3 I/O<G> F26 L4 I/O<D> I/O<G> (Sheet QL6325 Eclipse Data Sheet Rev C Function 516 PBGA Function I/O<H> L11 P5 GND I/O<H> L12 P6 GND V <H> CCIO L13 P11 GND GND L14 P12 GND GND ...
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... QL6325 Eclipse Data Sheet Rev C 516 PBGA Function 516 PBGA Function 516 PBGA U1 W25 I/O<H> U2 W26 I/O<H> I/O<H> I/O<H> U5 I/O<H> GND U21 Y5 GND U22 Y6 N/C U23 Y21 I/O<C> U24 Y22 I/O<C> U25 Y23 I/O<C> U26 Y24 I/O<C> V1 Y25 I/O<H> V2 Y26 IOCTRL<H> V3 AA1 IOCTRL<H> V4 AA2 I/O<H> V5 N/C AA3 V6 AA4 V <H> CCIO V21 ...
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... PBGA Packaging Drawing © 2002 QuickLogic Corporation Figure 29: 516 PBGA Packaging Drawing QL6325 Eclipse Data Sheet Rev C www.quicklogic.com • • • 37 • • • ...
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... QL6325 Eclipse Data Sheet Rev C Contact Information Telephone: 408 990 4000 (US) E-mail: Support: Web site: Revision History Revision Copyright Information Copyright © 2002 QuickLogic Corporation. All Rights Reserved. The information contained in this product brief, and the accompanying software programs are protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to make periodic modifications of this product without obligation to notify any person or entity of such revision ...