VT6508 VIA, VT6508 Datasheet

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... VIA Technologies, Inc. 8 RMII P ORTS OF E THERNET REVISION ‘D’ DATASHEET VIA Technologies, Inc. VT6508 10/100B S C WITCH (Preliminary) ISSUE 1: Nov 23, 1999 1 Preliminary VT6508 Datasheet -T/TX ASE ONTROLLER ...

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... Offices: 1045 Mission Court Fremont, CA 94539 USA Tel: (510) 683-3300 Fax: (510) 683-3301 Online Services: BBS : 886-2-2186408 FTP : FTP.VIA.COM.TW HTTP:WWW.VIA.COM.TW Preliminary VT6508 Datasheet th 8 Floor, No. 533 Chung-Cheng Rd., Hsin-Tien Taipei, Taiwan ROC Tel: Fax: –or- WWW.VIATECH.COM IGHTS ...

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... IGURES AND ABLES R H ................................................................................................................................ 5 EVERSION ISTORY F ................................................................................................................................................ 6 EATURES B D ...................................................................................................................................... 9 LOCK IAGRAM FIGURE 1: FUNCTION BLOCK DIAGRAM OF VT6508. (NOTE THAT SOME INTERFACE SIGNALS ARE ONLY AVAILABLE IN VT6509 OF 208-PIN PQFP PACKAGE.).............................. ................................................................................................................................... 10 INOUT IAGRAM FIGURE 2: PINOUT DIAGRAM OF VT6508. ...................................................................................... .................................................................................................................................. 11 IN ESCRIPTIONS D VT6508B S EFINITION OF TRAPPING Pin ...

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... VIA Technologies, Inc IGURES AND ABLES Figure 1: Function Block Diagram of VT6508. (Note that some interface signals are only available in VT6509 of 208-pin PQFP package.)..................................................9 Figure 2: Pinout Diagram of VT6508. .......................................................................10 Figure 3. SRAM memory layout................................................................................17 Figure 4. Data structure of forwarding table slot........................................................17 Figure 5. Data structure of embedded link node.........................................................17 Figure 6 ...

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... VIA Technologies, Inc EVERSION ISTORY Reversion Date V0.01 11/23/1999 Preliminary VT6508 Datasheet Reason for change First release version 5 By Murphy Chen ...

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... Support chip initialization through EEPROM or by strapping only Supports I C EEPROM interface for customized configuration - Supports LED serial-out in the strapping-only initialization mode 50MHz internal reference clock rate l 83~100MHz SSRAM clock rate, typically 83MHz l Single +3.3V supply, 0.3 m TSMC CMOS technology l 128-pin PQFP package l Preliminary VT6508 Datasheet 6 ...

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... VIA Technologies, Inc. Preliminary VT6508 Datasheet 7 ...

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... MII interface LED Serial-Out Control Ethernet RMAC RMAC LED serial-out bus Figure 1: Function Block Diagram of VT6508. (Note that some interface signals are only available in VT6509 of 208-pin PQFP package.) 99/12/09 Preliminary VT6508 Datasheet 32-bit SRAM bus SRAM Control Queue Control (flow control) Output ...

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... MDIO 118 MDC 119 TXD1_0 120 TXD0_0 121 TXEN_0 122 VSS 123 CSDV_0 124 RXD0_0 125 RXD1_0 126 TXD1_1 127 TXD0_1 128 99/12/09 VT6508 Figure 2: Pinout Diagram of VT6508. 10 Preliminary VT6508 Datasheet ...

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... Serial LED Serial-Out Data Output (if strapping SD25 is low) Management Interface (MI) Clock Output O Management Interface (MI) Data I/O I/O 50MHz Main Reference Clock I SRAM Reference Clock I The suggested clock rate is 83MHz or more high for non-blocking requirement. SYSTEM RESET I Positive 3.3V supply to the core digital logic. Positive 3.3V supply to all I/O pads. -11- Preliminary VT6508 Datasheet Description ...

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... In none speedup mode, EEC = 78.125K Hz, LED period = 50ms. In speedup mode for testing, EEC = 2.778MHz, LED period = 1ms without one-second flash. Ground supply to the core digital logic. Ground supply to all I/O pads. P TRAPPING INS *Note that the default strapping bit value is “1”. (default) -12- Preliminary VT6508 Datasheet ...

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... SD17 == 1, port (6,7) no trunking (default) 0, port (6,7) in trunking mode. To simplify layout, trunk group (6,7) can connect with neighboring (right-side) VT6508’ s trunk group (0,1) in on-board manner. Note that on-board trunk ports do not need auto-polling and they must be full-duplex & 100Mbps ports & forced flow control enable mode. ...

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... Disable TEST mode: SD[30] DIS_TEST_MODE == 1 => disabled (default) DIS_TEST_MODE == 1 => enabled Disable Latchup Mode: SD[31] DIS_LATCH_UP_MODE == 1’ b1 => disable Latchup mode (default) DIS_LATCH_UP_MODE == 1’ b0 => enable Latchup mode, all output only IO PADs are in tri-state after reset. Preliminary VT6508 Datasheet EEIO/EEC. (default) LEDIO/LEDC. -14- ...

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... D ENERAL ESCRIPTION The VT6508 is a low-cost switch engine chip implementation ports 10/100Mbps Ethernet switch system for IEEE 802.3 and IEEE 802.3u networks. Each port can be either auto-sensing or manually selected via EEPROM configuration to run at 10Mbps or 100Mbps speed rate, full or half duplex mode. ...

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... ACKET UFFERS AND VT6508 provides a 32-bit SRAM interface for packet buffering and maintaining address table and per-port output link lists. Each packet buffer is a 1536-byte contiguous memory block in SRAM, and it also contains to a 8-byte link node data structure in every buffer’s tail. A link ...

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... Figure 3. SRAM memory layout age forward reserved count source packet byte port count ports bit mask -17- Preliminary VT6508 Datasheet address offset: 05FFH embedded link node 05F8H packet content 0000H 40 39 MAC tag mask 10 9 destination next packet buffer ID ...

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... Every packet buffer is 1.5K bytes with a corresponding embedded link node in the tailing 8 bytes. The embedded link nodes are used to construct output queues, one queue for each output port. Its structure is shown in Figure 5, composed of: (1) bits 9..0: Next Packet Buffer ID (2) bits 19..10: Destination Ports Bit Mask Preliminary VT6508 Datasheet static[1:0] (0,1) (1,1) (1, ...

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... The number of packet buffers is determined by the configured SRAM size, listed as follows: SRAM Size maximum # of packet buffers 2.3 RMII I NTERFACE The VT6508 can directly connect port RMII PHY device through the reduced MII (RMII) interface to construct a small-sized system board. The signals of RMII interface are described as follows: 2 ...

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... Read PHY Auto-negotiation Complete bit (Reg1. auto-negotiation is completed (Reg1.5)=”1”, then go to step8. - else if auto-negotiation is not completed (Reg1.5)=”0”, then go to step10. Preliminary VT6508 Datasheet st time st time ...

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... F C LOW ONTROL In VT6508, there are three policies of resource management for different objectives: (1) flow control for full-duplex ports Objective: slow down the input traffic without incurring any drops. (2) backpressure for half-duplex ports Objective: slow down the input traffic with intended collision and the Ethernet backoff mechanism ...

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... XOFF state, respectively. If the source port is within XOFF window as an XOFF event arrives, an flow control frame with pause time = 0xffff will be sent out. If the source port is within XON window, the arriving XON event will be ignored. Preliminary VT6508 Datasheet -22- ...

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... VIA Technologies, Inc. XOFF_WINDOW[ Figure 6. XON/XOFF Window Concept. Congestion-Control Operations The starvation control threshold VT6508. Let be the Virtual Free Buffer Count, where based on . Within XOFF window, the corresponding congestion-control operations are as follows: (1) flow control operation As a unicast or broadcast packet, enqueued by Input Control, violates the congestion control constraints, Queue Control will assert a trigger to its source port’ ...

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... VIA Technologies, Inc. XON/XOFF Thresholds Selection In VT6508, the XON threshold is fixed and programmable. Basically, the XON threshold is equal to half of total number of buffers – 10. The XOFF threshold is adaptive and has two objectives: (1) Prevent buffers are exhausted by some hungry port for unbalanced traffic condition. So, XOFF threshold > ...

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... Default D = 2x9 + for SRAM size of 256KB £ Free memory count £ buffers necessary to be reserved for private policy. XOFF condition: ( (£ X ¡ Ø (max{£ D}+C) ) and (R XON condition: Preliminary VT6508 Datasheet # of Free Buffers uncongestion area XON watermark (fixed) XOFF watermark (adaptive) ...

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... VIA Technologies, Inc. ( (£ X > XON_Thred) XON_Thred = (1/2) x (MaxBufferNo + MaxXOFF - 20) Preliminary VT6508 Datasheet -26- ...

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... S ROADCAST TORM In VT6508, the feature of broadcast storm filtering is based on the above congestion control, and subjects to incoming broadcast packets. When an incoming broadcast packet is first enqueued by the Input Control of the source port, Queue Control will check if any one of its destination output ports is in XOFF window. If yes, it will trigger flow control to source port ...

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... Note that EEPROM device id and address must be 7’b1010_001. 2.7 T RUNKING There are two trunk groups in VT6508, one is port (0,1), another is port (6,7). Each one can be enabled individually. The trunking load balance algorithm is as follows: Assume DMAC=12'h000000000002, source_port_id = 4'b0001. DMAC_forwarding_entry_address = hash algorithm(DMAC resident slot# Assume the above value is 12'b000000011010 after lookup for DMAC = 12'h000000000002 ...

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... Let dest_bit = DMAC_forwarding_entry_address[4] xor source_port_id[0]. If the DMAC refers to a trunk port of the trunk group (0,1), the selected outgoing trunk port is port 0 + dest_bit. If the DMAC refers to a trunk port of the trunk group (6,7), the selected outgoing trunk port is port 6 + dest_bit. Preliminary VT6508 Datasheet -29- ...

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... VIA Technologies, Inc VT6508 SRAM ADDRESS MAPPING TABLE HE 128-pin 32bit mode ( 1 Bank of 32Kx32, 64Kx32): 6508 Pad(64bit mode) Internal 64bit linear Address IA15 SA15 = IA14 IA14 SA14 = IA13 IA13 SA13 = IA12 IA12 SA12 = IA11 IA11 SA11 = IA10 IA10 SA10 = IA9 IA9 ...

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... CHIP_CFG[45]: TRUNK_MODE[3] CHIP_CFG[42]: RMII_SPEED_CFG[9] CHIP_CFG[44]: RMII_SPEED_CFG[8] CHIP_CFG[46]: SRAM_NUM CHIP_CFG[47]: SRAM_TYPE[0] CHIP_CFG[48]: DIS_DROP_STARV CHIP_CFG[51:49]: MII_PORT_CFG CHIP_CFG[52]: SRAM_32BIT_MODE CHIP_CFG[53] DIS_SHORT_PREAM CHIP_CFG[54]: PHY_ADDRESS_SEQ CHIP_CFG[55]: RMII_SPEED_ARB CHIP_CFG[56]: DIS_9_PORT_LED_MODE CHIP_CFG[62:57]: (reserved with value 1’ s) CHIP_CFG[63]: DIS_INIT_DBG_MODE Preliminary VT6508 Datasheet M AP Name CHIP_CFG -31- Bits Default R/W Value [63:0] by R/W strapping ...

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... The valid value is 1..255. The default inter-aging time value is 50ms for an entry by default strapping so that the forwarding table entries (4K slots) can be aged completely in about 5 minutes. Preliminary VT6508 Datasheet EN_LED_OUT [0] CPU_SOFT_RESET [0] XON_THRED [9:0] PRIVATE_BUF_SIZE [4:0] QUEUE_ID [3:0] ...

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... Tag[15:8] Tag[7:0] ßà MAC[47:40] 0A- destination MAC object 0FH 0AH: DMAC[47:40], 0BH: DMAC[39:32], … , 0FH: DMAC[7:0]. A write to this register will make the corresponding CRC-map lower 11-bit hash key and upper 37-bit tag shown in HASH_CONTENT. Preliminary VT6508 Datasheet AGING_INDEX [10:0] AGING_STATUS [0] HASH_ALG [1:0] DMAC_OBJ [47:0] -33- 0 R/W ...

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... MCAST_DPM [7:0] 1CH: MCAST_DPM [9:8] for multicast packet lookup miss broadcast control 1DH selection of CPU_PM usage 0: select cpu port to use CPU_PM for lookup 1: select MII port to use CPU_PM for lookup Preliminary VT6508 Datasheet HASH_CAL_STATU [0] S HASH_KEY [10:0] HASH_RESULT LOOKUP_MISS_MA [9:0] SK ...

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... Drop On Value 1: the corresponding port’ s drop feature is enabled. Any incoming packets destining to any one port in congestion will be dropped by Forwarding Control by setting port mask = 0. Value 0: the port’ s drop feature is disabled. This signal is from TMAC. Preliminary VT6508 Datasheet CPU_PM [8:0] SPECIAL_CTL [7:0] CPU_FWD_CFG [2 3:0] ...

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... PHY control 00H CPU command port ID Normally the working port ID for CPU direct read/write. It also shows the working port ID for auto-polling debugging mode. 01H CPU command PHY REG number Preliminary VT6508 Datasheet CONGEST_ON [9:0] XOFF_WINDOW [9:0] PORT0_STP_STATE [1:0] PORT1_STP_STATE [1:0] PORT2_STP_STATE [1:0] PORT3_STP_STATE [1:0] ...

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... The last data byte read from EEPROM is stored in this register for CPU read. Note that the last data byte written to EEPROM is stored in an internal register that is also located in this address for CPU write, but not readable. Preliminary VT6508 Datasheet PHYDATA [15:0] PHYCMD [3:0] ...

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... Note: value 0 means “ masked” , value 1 means “ not masked” . The default is “ masked” so that software has to poll IRQSTS to check if there are any pending interrupts. Preliminary VT6508 Datasheet EEDEVADDR [7:0] EESTS [3:0] IRQSTS ...

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... byte, write the last one byte data first, and then write another byte for dummy padding. Packet Abort 11H Writing 1’ this register will drop an incoming packet ready to be read by CPU. Reading this register will clear this register as 1’ b0. Preliminary VT6508 Datasheet SRAMADDR [16:0] SRAMDATA [63:0] SRAMCMD [1:0] ...

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... Revision ID 1000H MAC & I/O Control Module of Port 0 00H configurable preamble bytes 01H configurable frame gap in di bits for 1st interval IFG_CFG Preliminary VT6508 Datasheet PKT_DATA SWITCH_MAC SWITCH_MAC SWITCH_MAC SWITCH_MAC SWITCH_MAC SWITCH_MAC SRAM_AUTO_TEST [2:0] complete or idle ...

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... Note that the broadcast domain is determined by the CPUIO_CFG[1] and 9 bits of all Ethernet ports’ IO_CFG[1]. If IO_CFG[1]==0, this Ethernet port must be not within the broadcast domain. Preliminary VT6508 Datasheet BOFFCFG nd collided st and rd collision, i.e. the ...

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... It is cleared automatically after CPU read. 12H- received bad packet count (Counter 2) 13H It is cleared automatically after CPU read. 14H- drop packet counter(Counter 3) 15H It is cleared automatically after CPU read. Preliminary VT6508 Datasheet FREE_BUF_ADDR1 [12:0] FREE_BUF_ADDR2 [12:0] EVENT_MASK [14:0] RCV_GOOD_PKT [15:0] RCV_BAD_PKT [15:0] DROP_PKT [15:0] ...

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... Packet source port ID 03H CPU can check the incoming packet’ s source port ID via the 3-bit register PKT_SRC_PORT before starting to read it useful to the spanning tree algorithm. Preliminary VT6508 Datasheet XMT_GOOD_PKT [15:0] XMT_BAD_PKT [15:0] XMT_ABORT_PKT [15:0] DEQUEUED_BUF_A ...

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... CPUIO_CFG[0] = 1.) 0: not ready (default) 1: ready Note that if CPU XOFF window, it will be not ready with WR_PKT_STATUS[2]==1. CPU IO always uses flow control mechanism with displaying XON/XOFF status in XOFF_WINDOW[9] of Forwarding Control. Preliminary VT6508 Datasheet CPUIO_CFG [2:0] FREE_BUF_ADDR [11:0] DEQUEUED_BUF_A [11:0] DDR WR_PKT_STATUS ...

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... Input leakage current IL I Tristate leakage current OZ I Power supply current CC S PECIFICATIONS ATINGS Min 0 0 -55 -0.5 = 3.1 - 3.6V) -0.5 Min Max -0.50 0.8 2 0.45 2 +/-10 - +/-20 TBD - -45- Preliminary VT6508 Datasheet Max Unit 100 o C 125 o C 5.5 Volts V + 0.5 Volts CC Unit Condition =4.0mA =-1.0mA OH uA 0<V < 0.45<V <V OUT CC ...

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... TXD TX_EN output delay - Management Interface (MI) Timing Characteristics Parameter min MDC cycle time - MDC high time 180 MDC low time 180 MDIO setup time 30 (source by PHY) MDIO hold time 0 (source by PHY) Preliminary VT6508 Datasheet Min Max 3.135 0 HOLD MIN 2 1 type max 20 ...

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... Start Condition setup time Start Condition 6.4 hold time Stop Condition setup time Stop Condition 6.4 hold time Read Data In 0 setup time Read Data In 0 hold time EEIO Data out 2.6 delay Write Cycle time - Preliminary VT6508 Datasheet - 300 typ max 0 78.12 6.4 - 6 ...

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... VIA Technologies, Inc ACKAGE ECHANICAL Preliminary VT6508 Datasheet S PECIFICATIONS VT6508 -48- ...