GM2121 GMI, GM2121 Datasheet
GM2121
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GM2121 Summary of contents
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... No. 24, Ln 123, Sec 6, Min-Chung E. Rd. • Taipei • Taiwan • Tel: (2) 2791-0118 • Fax: (2) 2791-0196 143-37 Hyundai Tower • Unit 902 • Samsung-dong • Kangnam-gu • Seoul • Korea • 135-090 • Tel: (82-2) 553-5693 • Fax: (82-2) 552-4942 www.genesis-microchip.com / info@genesis-microchip.com gm2121 LVDS Transmitter Publication Number: C2121-DAT-01F Publication Date: December 2002 Genesis Microchip Inc ...
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The following are trademarks or registered trademarks of Genesis Microchip, Inc Genesis , Genesis Display Perfection TM SureSync , Adaptive Backlight Control™, Faroudja Other brand or product names are trademarks of their respective holders. © Copyright 2002 Genesis ...
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... Overview ........................................................................................................................................8 1.1 gm2121 System Design Example..........................................................................................8 1.2 gm2121 Features ...................................................................................................................9 2 GM2121 Pinout ............................................................................................................................10 3 GM2121Pin List ...........................................................................................................................11 4 Functional Description .................................................................................................................16 4.1 Clock Generation.................................................................................................................16 4.1.1 Using the Internal Oscillator with External Crystal ........................................................17 4.1.2 Using an External Clock Oscillator.................................................................................19 4.1.3 Clock Synthesis ...............................................................................................................20 4.2 Chip Initialization................................................................................................................21 4.2.1 Hardware Reset ...............................................................................................................21 4.2.2 Correct Power Sequencing ..............................................................................................22 4.3 Analog to Digital Converter ................................................................................................22 4 ...
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... Pulse Width Modulation (PWM) Back Light Control ................................................45 5 Electrical Specifications ...............................................................................................................46 5.1 Preliminary DC Characteristics ...........................................................................................46 5.2 Preliminary AC Characteristics ...........................................................................................48 5.3 External ROM Interface Timing Requirements ..................................................................49 6 Ordering Information ...................................................................................................................50 7 Mechanical Specifications............................................................................................................51 C2121-DAT-01F gm2121 Preliminary Data Sheet 4 December 2002 ...
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... Pin Connection for RGB Input with HSYNC/VSYNC...................................................23 Table 12. ADC Characteristics........................................................................................................24 Table 13. Supported LVDS 24-bit Panel Data Mapping.................................................................34 Table 14. Supported LVDS 18-bit Panel Data Mapping.................................................................34 Table 15. gm2121 GPIOs and Alternative Functions .....................................................................41 Table 16. Bootstrap Signals.............................................................................................................41 Table 17. Instruction Byte Map.......................................................................................................43 Table 18. Absolute Maximum Ratings............................................................................................46 Table 19. ...
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... Correct Power Sequencing ..............................................................................................22 Figure 11. Example ADC Signal Terminations................................................................................23 Figure 12. gm2121 Clock Recovery .................................................................................................24 Figure 13. ADC Capture Window ....................................................................................................25 Figure 14. Some of gm2121 built-in test patterns ............................................................................26 Figure 15. Factory Calibration and Test Environment .....................................................................26 Figure 16. HSYNC Delay.................................................................................................................27 Figure 17. Active Data Crosses HSYNC Boundary .........................................................................27 Figure 18. ODD/EVEN Field Detection...........................................................................................28 TM Figure 19 ...
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... C2121-DAT-01A Initial release • Corrected Pin out changes as follows: C2121-DAT-01B Figure 2, gm2121 Pin out Diagram (Pin #102 to 116) o Table 2, RCLK PLL pins o Table 7, Power & Ground Pins for ADC Sampling Clock DDS o Table 8, Power & Ground Pins for Display Clock DDS ...
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... System Design Example Figure 1 below shows a typical dual interface LCD monitor system based on the gm2121. Designs based on the gm2121 have reduced system cost, simplified hardware and firmware design and increased reliability because only a minimal number of components are required in the system. ...
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... Horizontal and vertical stretch of OSD menus • Blinking, transparency and blending Built in Test Pattern Generator C2121-DAT-01F gm2121 Preliminary Data Sheet On-chip Microcontroller • Requires no external micro-controller • External parallel ROM interface allows ...
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... The gm2121 is available in a 160-pin Plastic Quad Flat Pack (PQFP) package. Figure 2 provides the pin locations for all signals. ROM_DATA5 1 2 ROM_DATA4 3 ROM_DATA3 4 ROM_DATA2 5 ROM_DATA1 6 ROM_DATA0 7 ROM_OEn 8 GPIO22/HCLK 9 GPIO16/HFSn 10 GPIO20/HDATA3 GPIO19/HDATA2 11 GPIO18/HDATA1 12 GPIO17/HDATA0 13 14 RVDD_3.3 15 CRVSS 16 GPIO21/IRQn 17 RESETn 18 GPIO15/DDC_SCL 19 GPIO14/DDC_SDA 20 CVDD_2.5 ...
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... GND2_ADC pin on system board (as close as possible to the pin). ADC input horizontal sync input. [Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] ADC input vertical sync input. [Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] RCLK PLL Pins Table 2. 11 gm2121 Preliminary Data Sheet December 2002 ...
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... General-purpose output signal GPO General-purpose output signal GPO General-purpose output signal GPO General-purpose output signal C2121-DAT-01F System Interface and GPIO Signals 12 gm2121 Preliminary Data Sheet December 2002 ...
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... ROM_DATA2 4 I ROM_DATA1 5 I ROM_DATA0 6 I ROM_OEn 7 O External PROM data Output Enable C2121-DAT-01F Display Output Port Table 4. Parallel ROM Interface Port 13 gm2121 Preliminary Data Sheet December 2002 ...
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... P Digital power for the Destination DDS. Connect to 3.3V supply. VSS_DDDS 111 G Digital ground for the Destination DDS. C2121-DAT-01F Reserved Pins Table 6. 14 gm2121 Preliminary Data Sheet December 2002 ...
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... Must be directly connected to the system ground plane. AVSS_LV_O 76 G Analog ground for on-chip LVDS transmitter. Must be directly connected to the system ground plane. C2121-DAT-01F gm2121 Preliminary Data Sheet I/O Power and Ground Pins 15 December 2002 ...
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... Figure 7 below. This option is selected by connecting a 10KΩ pull-up to ROM_ADDR13 (refer to Table 17). See also Table 12. 2. Host Interface Transfer Clock (HCLK) The gm2121 TCLK oscillator circuitry is a custom designed circuit to support the use of an external oscillator or a crystal resonator to generate a reference frequency source for the gm2121 device. C2121-DAT-01F ...
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... The oscillator circuit also minimizes the overdrive of the crystal, which reduces the aging of the crystal. When the gm2121 is in reset, the state of the ROM_ADDR13 pin is sampled. If the pin is left unconnected (internal pull-down) then internal oscillator is enabled. In this mode a crystal resonator is ...
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... Figure 6. The loading capacitance (C combination of C and C and is calculated capacitance C is the effective capacitance between the XTAL and TCLK pins. For the gm2121 this is shunt approximately 9 pF. C and C are a parallel combination of the external loading capacitors ( ...
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... Using an External Clock Oscillator Another option for providing the reference clock is to use a single-ended external clock oscillator. When the gm2121 is in reset, the state of the ROM_ADDR13 is sampled. If ROM_ADDR13 is pulled high by connecting to VDD through a pull-up resistor (10KΩ recommended, 15KΩ maximum) then external oscillator mode is enabled ...
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... Clock Synthesis The gm2121 synthesizes all additional clocks internally as illustrated in Figure 8 below. The synthesized clocks are as follows: 1. Main Timing Clock (TCLK) is the output of the chip internal crystal oscillator. TCLK is derived from the TCLK/XTAL pad input. 2. Reference Clock (RCLK) synthesized by RCLK PLL (RPLL) using TCLK as the reference. ...
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... On-chip Clock Domains 21 gm2121 Preliminary Data Sheet December 2002 ...
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... RVDD-CVDD T CVDD->RESETn 4.3 Analog to Digital Converter The gm2121 chip has three ADC’s (analog-to-digital converters), one for each color (red, green, and blue). C2121-DAT-01F > all times. This is illustrated in Figure 10. ...
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... ADC Pin Connection The analog RGB signals are connected to the gm2121 as described below: Pin Connection for RGB Input with HSYNC/VSYNC Table 12. Pin Name Red+ Red Red- Terminate as illustrated in Figure 11 Green+ Green Green- Terminate as illustrated in Figure 11 Blue+ Blue Blue- Terminate as illustrated in Figure 11 ...
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... This may introduce image artifacts. However, the image is clear enough to allow the user to change the display properties. The gm2121 ADC has a built in clamp circuit for AC-coupled inputs. By inserting series capacitors (about 10 nF), the DC offset of an external video source can be removed. The clamp pulse position and width are programmable ...
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... IP_CLKs (equivalent to a pixel count). In the vertical direction it is defined in lines. All the parameters beginning with “Source” are programmed gm2121 registers values. Note that the input vertical total is solely determined by the input and is not a programmable parameter. Reference Point Figure 13 ...
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... OSD controller can be used to produce other patterns. Figure 14. The DDC2Bi port can be used for factory testing. The factory test station connects to the gm2121 through the Direct Data Channel (DDC) of the DSUB15 connector. Then, the PC can make gm2121 display test patterns (see section 4 ...
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... Delayed horizontal sync may be used to solve a potential problem with VSYNC jitter with respect to HSYNC. VSYNC and HSYNC are generally driven active coincidentally, but with different paths to the gm2121 (HSYNC is often regenerated from a PLL result, VSYNC may be seen earlier or later. Because VSYNC is used to reset the line counter and HSYNC is used to increment it, any difference in the relative position of HSYNC and VSYNC is seen on-screen as vertical jitter ...
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... HS window VS - even VS - odd Figure 18. C2121-DAT-01F Window Start Window End ODD/EVEN Field Detection 28 gm2121 Preliminary Data Sheet December 2002 ...
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... The gm2121 performs measurements to determine the image boundary. This information is used when programming the Active Window and centering the image. 4.5.9 Image Auto Balance The gm2121 performs measurements on the input data that is used to adjust brightness and contrast. TM 4.6 RealColor Digital Color Controls The gm2121 provides high-quality digital color controls. These consist of a subtractive "black level" ...
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... Horizontal and Vertical Shrink The gm2121 provides an arbitrary horizontal and vertical shrink down to (50 pixel/line) of the original image size. This allows the gm2121 to capture and display images one VESA standard format larger than the native display resolution. For example, UXGA may be captured and displayed on an SXGA panel ...
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... The LUT has bypass enable. If bypassed, the LUT does not require programming. 4.10 Display Output Interface The Display Output Port provides data and control signals that permit the gm2121 to connect to a variety of flat panel or CRT devices. The output interface is configurable for 18 or 24-bit RGB pixels, either single or double pixel wide ...
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... Vertical Blanking (Back Porch) Vertical Blanking (Front Porch) DH_TOTAL DH_ACTIVE_WIDTH Display Windows and Timing XXX rgb0 rgb1 rgb2 XXX Single Pixel Width Display Data 32 gm2121 Preliminary Data Sheet DV_VS_END DV_BKGND_START DV_ACTIVE_START DV_ACTIVE_LENGTH DV_BKGND_END ** DEN is not asserted during vertical blanking rgb3 rgb4 December 2002 ...
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... OR/OG/OB (Output) Figure 22. 4.10.3 Panel Power Sequencing (PPWR, PBIAS) gm2121 has two dedicated outputs PPWR and PBIAS to control LCD power sequencing once data and control signals are stable. The timing of these signals is fully programmable. TMG1 PPWR Output Panel Data and Control Signals PBIAS Output < ...
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... EMI reducing components and shielding. 4.13 OSD The gm2121 has a fully programmable, high-quality OSD controller. The graphics are divided into “cells” pixels in size. The cells are stored in an on-chip static RAM (4096 words by 24 bits) and can be C2121-DAT-01F ...
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... This permits a good compression ratio while allowing more than 16 colors in the image. Some general features of the gm2121 OSD controller include: OSD Position – The OSD menu can be positioned anywhere on the display region. The reference point is Horizontal and Vertical Display Background Start (DH_BKGND_START and DV_BKGND_START in Figure 20) ...
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... On-Chip Microcontroller (OCM) The gm2121 on-chip microcontroller (OCM) serves as the system microcontroller. It programs the gm2121 and manages other devices in the system such as the keypad, the back light and non-volatile RAM (NVRAM) using general-purpose input/output (GPIO) pins. The OCM can operate in two configurations, Standalone configuration and Full-Custom configuration, as illustrated in Figure 25 ...
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... Standalone Configuration Standalone configuration offers the most simple and inexpensive system solution for generic LCD monitors. In this configuration the OCM executes firmware stored internally in gm2121. The baud rate for serial communication (in standalone configuration) is determined by two bootstrap resistors on ROMADDR11 (TCLK_SEL1, pin 145) and ROMADDR10 (TCLK_SEL0, pin 146). The on-chip firmware provides all the standard functions required in a high-quality generic LCD monitor ...
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... Both instructions and data are fetched from external ROM on a cycle-by-cycle basis. The external ROM access speed on the parallel port is determined by the gm2121 internal OCM_CLK, which is derived from the TCLK result, the external ROM device’s access speed requirements are directly related to the TCLK frequency. For the detailed timing requirements see section 5.3 “ ...
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... UART Interface The gm2121 OCM has an integrated Universal Asynchronous Remote Terminal (UART) port that can be used as a factory debug port. In particular, the UART can be used to 1) read / write chip registers, 2) read / write to NVRAM, and 3) read / write to FLASH ROM. ...
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... For DDC2Bi communication over the analog VGA connector pins GPIO22/HCLK and GPIO16/HFSn should be connected to the DDC clock and data pins of the analog DSUB15 VGA connector. gm2121 contains serial to parallel conversion hardware, that is then accessed by firmware for interpretation and execution of the DDC2Bi command set. Bootstrap option ROM_ADDR12 (pin 142) is used to select the pin pair to be used for DDC2Bi communication ...
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... OCM UART data in/out signals respectively. OCM external interrupt source (IRQINn). Write enable for external ROM if programmable FLASH device is used. Data and clock lines for master 2-wire serial interface to NVRAM when gm2121 is used in standalone configuration (section 4.14.1). General-purpose input/output signals. Open drain option via register setting. ...
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... These form an instruction byte, a device register address and/or one or more data bytes. This is described in Table 18. The first byte of each transfer indicates the type of operation to be performed by the gm2121. The table below lists the instruction codes and the type of transfer operation. The content of bytes that follow the instruction byte will vary depending on the instruction chosen ...
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... HCLK and either the master or slave can drive the HFSn line (open drain) depending on whether a read or write operation is being performed. The gm2121 operates as a slave on the interface. The 2-wire protocol requires each device be addressable by a 7-bit identification number. The gm2121 is initialized on power-up to 2-wire mode by asserting bootstrap pins HOST_PROTOCOL=0 and the device identification number on HOST_ADDR(6:0) on the rising edge of RESETn (see Table 17) ...
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... Figure 30. Please note that in all the above operations the operation code includes two address bits, as described in Table 18. 4.17 Miscellaneous Functions 4.17.1 Low Power State The gm2121 provides a low power state in which the clocks to selected parts of the chip may be disabled (see Table 20). C2121-DAT-01F ...
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... AC timing), and adjust brightness. Most LCD monitor manufactures currently use a microcontroller to provide these control signals. To minimize the burden on the external microcontroller, the gm2121 generates these signals directly. There are three pins available for controlling the LCD back light, PWM0 (GPIO0), PWM1 (GPIO1) and PWM2 (GPIO2) ...
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... T SOL T VAP and Power Consumption in Table 20, the typical case θ This equals 102 degrees Celsius gm2121 Preliminary Data Sheet MIN TYP MAX UNITS -0.3 3.6 -0.3 2.75 -0.3 5.5 -0.3 3.6 ±2.0 ±100 ...
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... I 3.3V_VDD I 3.3V_AVDD INPUTS V 2 GND IL V 2.4 IHC V GND ILC OUTPUTS V 2 GND gm2121 Preliminary Data Sheet (1) TYP MAX UNITS 1.57 1.726 W W 3.3 3.6 V 2.5 2. 597 656 mA 412 468 0 ...
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... Host Interface Port Timing Symbol MIN T 1.25 SHI T 1.25 SLO T 30 SDIS T 20 SDIH T 10 SDO3 48 gm2121 Preliminary Data Sheet = 16pF for all outputs. L Tap 2 Tap 3 Min Max Min Max (ns) (ns) (ns) (ns) -0.5 2.5 -1.5 1.5 -0.5 2.5 -1.5 1.5 -1.0 2.5 -2.0 1.5 -0.5 2.5 -1.5 1.5 TYP MAX Units 150 ns December 2002 ...
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... ACCmax MIRCO_CLK 3. T ≤ 83 MIRCO_CLK C2121-DAT-01F ACC A0 00F5 Address Asserted Data Latched External ROM Interface Timing Diagram 49 gm2121 Preliminary Data Sheet 00F6 A0 December 2002 ...
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... Ordering Information Order Code Application gm2121 SXGA C2121-DAT-01F gm2121 Preliminary Data Sheet Package Temperature Range 160-pin PQFP 0-70°C 50 December 2002 ...
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... Symbol Millimeter Min A 30.95 B 27. 3. 0. 0. gm2121 160-pin PQFP Mechanical Drawing 51 gm2121 Preliminary Data Sheet Inch Nom Max Min Nom Max 31.20 31.45 1.218 1.228 1.238 28.00 28.10 1.098 1.102 1.106 0.65 0.026 4.25 0.167 1.60 0.063 3.32 3.47 0.125 0.131 ...