PEEL18CV8ZJ-25 ICT, PEEL18CV8ZJ-25 Datasheet

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PEEL18CV8ZJ-25

Manufacturer Part Number
PEEL18CV8ZJ-25
Description
25ns CMOS programmable electrically erasable logic device
Manufacturer
ICT
Datasheet
1.PEEL18CV8ZJ-25.pdf (10 pages)

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
PEEL18CV8ZJ-25
Manufacturer:
TE
Quantity:
1 000
Features
General Description
The PEEL™18CV8Z is a Programmable Electrically Erasable
Logic (PEEL™) SPLD (Simple Programmable Logic Device)
that features ultra-low, automatic “zero” power-down operation.
The “zero power” (100 µA max. Icc) power-down mode makes
the PEEL™18CV8Z ideal for a broad range of battery-powered
portable equipment applications, from hand-held meters to PCM-
CIA modems. EE-reprogrammability provides both the conve-
nience of fast reprogramming for product development and quick
product personalization in manufacturing, including Engineering
Change Orders.
Figure 7 Pin Configuration
Ultra Low Power Operation
CMOS Electrically Erasable Technology
Application Versatility
- Vcc = 5 Volts ±10%
- Icc = 10 µA (typical) at standby
- Icc = 2 mA (typical) at 1 MHz
- Superior factory testing
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DIP
PLCC
Reprogrammable in plastic package
Reduces retrofit and development costs
Replaces random logic
Super set of standard PLDs
Pin-to-pin compatible with 16V8
Ideal for use in power-sensitive systems
CMOS Programmable Electrically Erasable Logic Device
I/CLK
TSSOP
GND
SOIC
I
I
I
I
I
I
I
I
10
2
3
4
5
6
7
8
9
1
PEEL™ 18CV8Z-25
20
19
18
17
16
15
14
13
12
11
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
1 of 10
The PEEL™18CV8Z is logically and functionally similar to
ICT’s 5 Volt PEEL™18CV8 and 3 Volt PEEL™18LV8Z. The
differences between the PEEL™18CV8Z and PEEL™18CV8
include the addition of programmable clock polarity, a product
term clock, and variable width product terms in the AND/OR
Logic Array.
Like the PEEL™18CV8, the PEEL™18CV8Z is logical superset
of the industry standard PAL16V8 SPLD. The PEEL™18CV8Z
provides additional architectural features that allow more logic to
be incorporated into the design. ICT’s JEDEC file translator
allows easy conversion of existing 20 pin PLD designs to the
PEEL™18CV8Z architecture without the need for redesign. The
PEEL™18CV8Z architecture allows it to replace over twenty
standard 20-pin DIP, SOIC, TSSOP and PLCC packages.
Figure 8 Block Diagram
Architectural Flexibility
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Programmable clock; pin 1 or p-term
Programmable clock polarity
Enhanced architecture fits in more logic
113 product terms x 36 input AND array
10 inputs and 8 I/O pins
12 possible macrocell configurations
Asynchronous clear, Synchronous preset
Independent output enables
20 Pin DIP/SOIC/TSSOP and PLCC
CLK MUX (Optional)
™
Commercial

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PEEL18CV8ZJ-25 Summary of contents

Page 1

... PAL16V8 SPLD. The PEEL™18CV8Z provides additional architectural features that allow more logic to be incorporated into the design. ICT’s JEDEC file translator allows easy conversion of existing 20 pin PLD designs to the PEEL™18CV8Z architecture without the need for redesign. The PEEL™ ...

Page 2

I/CLK ...

Page 3

Function Description The PEEL™18CV8Z implements logic functions as sum-of- products expressions in a programmable-AND/fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. User-configurable output structures in the form of I/O macrocells further ...

Page 4

I/O pin. Otherwise, the output buffer is switched into the high-impedance state. Under the control of the output enable term, the I/O pin can func- tion as a dedicated input, a dedicated output bi-directional I/ O. Opening ...

Page 5

Configuration Input/Feedback Select # Bi-directional I ...

Page 6

... PLD designs to the PEEL™18CV8Z, without the need for redesign. ICT supports a broad range of popular third party design entry systems, including Data I/O Synario and Abel, Log- ical Devices CUPL and others. ICT also offers (for free) its pro- prietary PLACE software, an easy-to-use entry level PC-based software development system. ...

Page 7

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Voltage Applied to Any Pin I Output Current O T Storage Temperature ST T Lead Temperature LT Operating Range Symbol Parameter Vcc Supply Voltage T ...

Page 8

A.C. Electrical Characteristics 8 Over the operating range Symbol Input to non-registered output Input to output enable Input to output disable t Clock to Output CO1 t Clock to ...

Page 9

... V Load R1 Output Technology CMOS TTL Ordering Information Part Number PEEL18CV8ZP-25 PEEL18CV8ZJ-25 PEEL18CV8ZS-25 PEEL18CV8ZT-25 PEEL18CV8ZPI-25 PEEL18CV8ZJI-25 PEEL18CV8ZSI-25 PEEL18CV8ZTI-25 Part Number Package P = 20-pin Plastic 300mil DIP J = 20-pin Plastic (J) Leaded Chip Carrier (PLCC 20-pin SOIC 300 mil Gullwing T = 20-pin TSSOP 170 mil Thevenin ...

Page 10

...

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