CY28341ZC-3 SpectraLinear Inc, CY28341ZC-3 Datasheet
CY28341ZC-3
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CY28341ZC-3 Summary of contents
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Universal Clock Chip for VIA™P4M/KT/KM400A DDR Systems Features • Supports VIA P4M/KM/KT/266/333/400A chipsets • Supports Intel Pentium 4, Athlon™ processors • Supports two DDR DIMMS • Provides: — Two different programmable CPU clock pairs — Six differential DDR pairs — ...
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Pin Description Pin Number Pin Name 3 XIN 4 XOUT 1 FS0/REF0 56 VTTPWRGD# REF1 44,42,38, DDRT (0:5) 36,32,30 43,41,37 DDRC (0:5) 35,31,29 7 SELP4_K7 / AGP1 VDDAGP 12 MULTSEL/PCI2 53 CPUT/CPUOD_T 52 CPUC/CPUOD_C 48,49 CPUCS_T/C 14,15,17,18 PCI (3:6) ...
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Pin Description (continued) Pin Number Pin Name 25 IREF 28 SDATA 27 SCLK 26 PD#/SRESET# 45 BUF_IN 46 FBOUT 5 VDDAGP 51 VDDC 16 VDDPCI 55 VDDR 50 VDDI 22 VDD_48M 23 VDD 34,40 VDDD 9 VSSAGP 13 VSSPCI ...
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Table 2. Command Code Definition Bit Description Block read or block write operation 1 = Byte read or byte write operation (6:0) Byte offset for byte read or byte write operation. For block read or block write ...
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Table 4. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit Description 29 Stop Serial Control Registers Byte 0: Frequency Select Register Bit @Pup Pin H/W Setting 21 5 H/W Setting 10 4 H/W Setting ...
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Byte 2: PCI Clock Register (continued PCI3 PCI2 PCI1 Byte 3: AGP/Peripheral Clocks Register Bit @Pup Pin# 24_48M 48MHz 24_48M 4 0 ...
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Byte 5: SDR/DDR Clock Register (continued) Bit @Pup Pin# Name 4 1 31,32 DDRT/ 35,36 DDRT/ 37,38 DDRT/ 41,42 DDRT/ 43,44 DDRT/C0 Byte 6: Watchdog Register Bit @Pup Pin ...
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Byte 7: Dial-a-Frequency Control Register N Bit @Pup Pin Reserved 6 0 N6, MSB N0, LSB Byte 8: Silicon Signature Register ...
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Swing Select Functions Through Hardware Board Target MULTSEL Trace/Term Ohm Watchdog Self-Recovery Sequence This feature is designed to allow the system designer to change frequency while the system is running and reboot the operation of the system ...
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P4 Processor SELP4_K7 Power-down Assertion (P4 Mode) When PD# is sampled low by two consecutive rising edges of CPU# clock then all clock outputs except CPU clocks must be held low on their next high to low transition. ...
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PD# CPUOD_T 133MHz CPUCS_T 133MHz CPUOD_C 133MHz CPUCS_C 133MHz PCI 33MHz AGP 66MHz USB 48MHz REF 14.318MHz DDRT 133MHz DDRC 133MHz Figure 4. Power-down Assertion Timing Waveform (In K7 Mode) Power-down Deassertion (K7 Mode) When deasserted PD# to high level, ...
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VID (0:3), SEL (0,1) VTT_PW RGD# PW RGD VDD Clock Gen Clock State State 0 Off Clock Outputs Off Clock VCO Figure 6. VTT_PWGD# Timing Diagram (with P4 Mode, SelP4_K7 = ...
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DDRT DDRC Table 10.Signal Loading Table Clock Name REF, 48MHz (USB), 24_48MHz AGP PCI_F DDRT/C, FBOUT CPUT/C CPUOD_T/C CPUCS_T Table 11.Group Timing ...
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CPU CLOCK 66.6MHz CPU CLOCK 100MHz CPU CLOCK 133.3MHz AGP CLOCK 66.6MHz PCI CLOCK 33.3MHz Rev 1.0, November 21, 2006 10ns 20ns t CSAGP t AP Figure 12. Group Timing Relationships CY28341-3 30ns Page ...
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Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DDA V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient Functional A T Temperature, Junction J ESD ESD Protection (Human Body HBM Model) ...
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AC Parameters (continued) Parameter Description P4 Mode CPU at 0.7V T CPUT/C Duty Cycle DC T CPUT/C Period PERIOD T /T CPUT/C Rise and Fall Times R F Rise/Fall Matching T /T Rise/Fall Time Variation CPUCS_T/C to ...
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AC Parameters (continued) Parameter Description 24 MHz T 24-MHz Duty Cycle DC T 24-MHz Period PERIOD 24-MHz Rise and Fall Times 24-MHz Cycle-to-Cycle Jitter CCJ REF T REF Duty Cycle DC T REF Period ...
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... Shrunk Small Outline package (SSOP)–Tape and Reel CY28341ZC–3 56-pin Thin Shrunk Small Outline package(TSSOP) CY28341ZC–3T 56-pin Thin Shrunk Small Outline package(TSSOP)–Tape and Reel Package Drawing and Dimensions 56-pin Thin Shrunk Small Outline Package, Type mm) Z56 Rev 1 ...
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While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result ...