CA82C55A-8CP Tundra Semiconductor, CA82C55A-8CP Datasheet
CA82C55A-8CP
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CA82C55A-8CP Summary of contents
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Series Components Manual ...
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... The information in this document is subject to change without notice and should not be construed as a commitment by Tundra Semiconductor Corporation. While reasonable precautions have been taken, Tundra Semiconductor Corporation assumes no responsibility for any errors that may appear in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Tundra Semiconductor Corporation ...
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... Corporate Profile Tundra Semiconductor Corporation is a privately-held, international, fabless semiconductor company focused on the design, development and delivery of bus-bridging components for embedded systems. Previously Newbridge Microsystems, a division of Newbridge Networks Corporation, Tundra commenced operations under its new name on December 18, 1995. Our mission statement is simple Tundra are committed to providing high-quality components that enable embedded systems designers to get to market faster with a more competitive product. Tundra takes a ‘ ...
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Table of Contents Product Index and Ordering 8000 Series Products Worldwide Sales Network ...
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... Product Index and Ordering............................................................................ 1-1 1.1 How to Order ....................................................................................... 1-1 1.2 Product Listing..................................................................................... 1-2 1.3 8000 Series Product Index ................................................................... 1-2 1.4 Ordering Information and Product Code ............................................. 1-3 1.5 Product Cross Reference...................................................................... 1-4 1.6 Package Codes and Mechanicals ......................................................... 1-6 2 8000 Series Products ......................................................................................... 2-1 2.1 CA80C85B........................................................................................... 2-1 2.2 CA82C37A......................................................................................... 2-17 2.3 CA82C52 ........................................................................................... 2-45 2.4 CA82C54 ........................................................................................... 2-69 2.5 CA82C55A......................................................................................... 2-91 2.6 CA82C59A....................................................................................... 2-123 3 Worldwide Sales Network ......................................................................... Sales-1 vii Table of Contents ...
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Product Index and Ordering 8000 Series Products Worldwide Sales Network Section ...
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... Product Listing on the following page. Then, use the Ordering Information and Product Code tables to help you find the product that matches your system requirements. If you require any assistance call the nearest Representative, Distributor, or our factory to place an order. (See “Worldwide Sales Network” on page Sales-1.) Tundra Semiconductor Corporation 1-1 ...
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... Programmable DMA Controller CA82C52 CMOS Serial Controller Interface CA82C54 Programmable Interval Timer CA82C55A Programmable Peripheral Interface CA82C59A Programmable Interrupt Controller Speed, Temperature Range and Package Codes are defined on the next page. This table shows only the most commonly available package options. Where a package lead count is not given, the device is either not available in that package available by special order only ...
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... For unusual, and/or specific packaging or processing requirements not covered by the standard product line, please contact our factory directly. Note that all products are not necessarily available in all packages. Tundra Semiconductor Corporation Ordering Information and Product Code Packaging P - Plastic DIP (PDIP) ...
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... CMOS Serial CA82C52 -16CN Controller Interface -5CP -5CN -8CP Programmable CA82C54 Interval Timer -8CN -10CP -10CN -5CP -5CN Programmable CA82C55A -8CP Peripheral -8CN Interface -10CP -10CN -8CP -8CN Programmable CA82C59A -10CP Interrupt -10CN Controller -10CM 1-4 Intel Harris Mitsubishi — ...
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... CMOS Serial CA82C52 -16CN Controller Interface -5CP -5CN -8CP Programmable CA82C54 Interval Timer -8CN -10CP -10CN -5CP -5CN Programmable CA82C55A -8CP Peripheral Interface -8CN -10CP -10CN -8CP -8CN Programmable CA82C59A -10CP Interrupt Controller -10CN -10CM Tundra Semiconductor Corporation AMD Samsung — ...
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... PDIP .150 TYP .125 .135 .015 MIN .008 .012 All dimensions in inches. Note: This package conforms to JEDEC reference MS-011, Variation AA. 1-6 8000 Series Product Catalogue 1.245 1.255 .055 .015 .065 .022 .600 .625 .530 .550 0 15 Tundra Semiconductor Corporation .100 TYP ...
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... Series Product Catalogue 28 - pin PDIP .150 TYP .125 .135 .150 MIN .008 .012 Tundra Semiconductor Corporation 1.445 1.450 .015 .100 TYP .022 .600 .625 .530 .550 All dimensions in inches Note: This package conforms to JEDEC reference MS-011, Variation AB. Package Codes and Mechanicals ...
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... PDIP .150 TYP .125 .135 .015 MIN .045 .055 1-8 2.055 2.065 .015 .022 .600 .625 .530 .550 .008 .012 All dimensions in inches Note: This package conforms to JEDEC reference MS-011, Variation AC. 8000 Series Product Catalogue .100 TYP 0 15 Tundra Semiconductor Corporation ...
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... Series Product Catalogue 1.6.2 PLCC (Package Code pin PLCC .045 TYP .450 .485 .455 .495 Tundra Semiconductor Corporation .485 .495 .450 .455 .045 x 45 TYP All dimensions in inches. Note: This package conforms to JEDEC reference MS-018, Variation AB. Package Codes and Mechanicals ...
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... All dimensions in inches. Note: This package conforms to JEDEC reference MS-018, Variation AC. 1-10 .685 .695 .650 .656 Tundra Semiconductor Corporation 8000 Series Product Catalogue .165 .180 .045 x 45˚ .045 x 45˚ .050 TYP .013 .021 .026 ...
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... Series Product Catalogue 1.6.3 SOIC (Package Code pin SOIC .002 .014 .006 .0125 28 1 Tundra Semiconductor Corporation .697 .728 .050 TYP .324 .350 .453 .500 All dimensions in inches Note: This package conforms to JEDEC reference MO-059, Variation AC. Package Codes and Mechanicals ...
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Product Index and Ordering 8000 Series Products Worldwide Sales Network Section ...
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... Figure 2-1: PDIP Pin Configurations Tundra Semiconductor Corporation The CA80C85B is an 8-bit microprocessor having complete pin and functional compatibility with industry standard 8085s and 8085As. In addition, it supports the special 8085 extended instruction set. The CA80C85B includes an on- board system controller, clock generator, serial I/O port and direct addressing capability to 64K bytes of memory ...
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... Tundra Semiconductor Corporation SOD B REG (8) C REG (8) D REG (8) E REG (8) H REG (8) L REG (8) REGISTER ARRAY SP: STACK POINTER (16) PC: PROGRAM COUNTER (16) INCREMENTER / DECREMENTER ADDRESS LATCH (16) ADDRESS BUFFER ( ADDRESS BUS Tundra Semiconductor Corporation DATA/ADDRESS BUFFER ( ADDRESS/DATA BUS ...
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... Tundra Semiconductor Corporation Name and Function High Address Bus: the most significant 8 bits of the memory address. Low Address and Data Bus: the least significant 8 bits of the memory address multiplexed with an 8-bit data bus. Address Latch Enable Out: This signal occurs during the first clock state of a machine cycle. ...
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... HLDA FF = SET HOLD NO T HOLD LAST MACHINE CYCLE HOLD YES RESET HLDA FF VALIDINT = 1 YES YES SET HALT = 1 INTA FF NO RESET INTE FF cycle, though the processor itself is active machine cycle. Tundra Semiconductor Corporation HOLD VALIDINT T HALT RESET HALT FF SET INTA FF RESET INTE FF ...
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... Leading Edge of WR WDL t X Rising to CLK Falling XKF Rising to CLK Rising XKR 1 Note Address Specs apply to IO and S1. Except and S are stable. 1 Tundra Semiconductor Corporation = 320 ns 150 pF CYC L Parameter , RD INTA , , ) RD WR INTA INTA WR to Data Valid - A are undefi ...
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... cycle whereas IO Tundra Semiconductor Corporation M 0 ...
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... Leading Edge of WR WDL t X Rising to CLK Falling XKF Rising to CLK Rising XKR 1 Note Address Specs apply to IO and S1. Except and S are stable. 1 Tundra Semiconductor Corporation = 167 ns 150 pF CYC L Parameter , RD INTA , , ) RD WR INTA INTA WR to Data Valid - A are undefi ...
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... cycle whereas IO Tundra Semiconductor Corporation M 0 ...
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... Figure 2-5: Timing Diagrams a) Clock Timing CLOCK TIMING X INPUT 1 CLK b) Read Operation READ OPERATION T CLK ALE t AL RD/INTA READY Tundra Semiconductor Corporation t XKF XKR LCK ADDRESS t AD ADDRESS LDR t AFR ...
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... DATA OUT ADDRESS LDW t WDL ARY t t RYS RYH T HOLD HDH HACK t HABF Tundra Semiconductor Corporation T T WAIT HOLD HOLD t HDH t HDS t HACK t HABE Tundra Semiconductor Corporation ...
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... T 1 CLK - ALE RD INTA t INH INTR t INS HOLD HLDA *NOTE: IO/M is also floating in a high-impedance state during this time Tundra Semiconductor Corporation HABF CALL INSTRUCTION BUS IN TRI - STATE (HIGH IMPEDANCE) t HDH t HDS t HACK CA80C85B T T ...
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... T = +25 C CYC and OUT –400 – Tundra Semiconductor Corporation Limits Units Min Max - - 0.25 V 2 2 –0.3 +0.8 V –0.3 +0.8 V 0.45 V 2.4 V 4.2 V Tundra Semiconductor Corporation ...
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... CMOS driver TTL device with a pull-up resistor, as shown in Figure 2-6(b). The clock low time must be greater than 80 ns for the 3 MHz device and 30 ns for the 6 MHz. Tundra Semiconductor Corporation – +160 C –0.3 to VDD +0.3 Volts 100mA 1 Watt ...
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... INTERRUPT MASKS INTERRUPT ENABLE PENDING INTERRUPTS Table 2-8: Interrupt Restart Address SERIAL DATA IN Interrupt TRAP RST7.5 RST6.5 RST5.5 INTR Tundra Semiconductor Corporation . RESET IN . INTA Restart Address (HEX) 24H 3CH 34H 2CH Dependent upon the instruction received on the bus during an INTA Tundra Semiconductor Corporation ...
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... High impedance state X - Don't care condition Tundra Semiconductor Corporation Extended Instructions and Condition Codes The CA80C85B Flag Register features two additional condi- tion code flags, for a total of seven. These are illustrated in Figure 2-9. The ten opcodes which comprise the extended ...
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... The contents of register L are moved to the memory none 3 10 location given by registers D and E. The contents of register H are Tundra Semiconductor Corporation Description (H) (L)=(H) (L) - (B) (C) (H) (L)=(H) (L) - (B) (C) (H) (L)=(H) (L) - (B) (C) (D) (E) = (H) (L) + (byte 2) (D) (E) = (SPH) (SPL) + (byte 2) L=((D) (E)); H=((D)( Tundra Semiconductor Corporation ...
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... DREQ Figure 2-1: PDIP Pin Configurations Tundra Semiconductor Corporation PROGRAMMABLE DMA CONTROLLER The CA82C37A is a high performance, programmable Direct Memory Access (DMA) controller offering pin-for- pin functional compatibility with industry standard 8237/8237A. It features four channels, each independently programmable, and is cascadable to any number of channels. ...
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... X 16) INTERNAL DATA BUS MODE REGISTER ( STATUS REGISTER (8) COMMAND REGISTER (8) MASK REGISTER (4) REQUEST REGISTER (4) Figure 2-3: CA82C37A Block Diagram Tundra Semiconductor Corporation OUTPUT BUFFER I/O BUFFER COMMAND CONTROL (4 X 16) I/O BUFFER TEMPORARY REGISTER (8) Tundra Semiconductor Corporation ...
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... DREQ I 0-3 21, 22 18, 19 Tundra Semiconductor Corporation Name and Function Low Address Bus: Bi-directional, 3-state signals. The 4 least significant address lines. Idle Cycle (Inputs). Addresses the CA82C37A control register to be loaded or read. Active Cycle (Outputs). Lower 4 bits of the transfer address. High Address Bus: 3-state output signals. The 4 most significant address lines representing the upper 4 bits of the transfer address ...
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... Temporary Registers, the Mode Register Counter and the First/Last Flip-Flop. The Mask Register is set to ignore DMA requests. The CA82C37A is in Idle Cycle following Reset. Power 10% DC Supply. Ground Tundra Semiconductor Corporation (Output). is activated when the word count EOP low terminates active DMA service. An EOP inputs. EOP Tundra Semiconductor Corporation ...
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... CPU processes. The device provides operating modes to carry out both single byte and block transfers of data. An operational flowchart of the CA82C37A is shown in Figure 2-4. Tundra Semiconductor Corporation FUNCTIONAL DESCRIPTION The organization of the CA82C37A is shown in the block diagram composed of three logic blocks, a series of internal registers and a counter section ...
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... Figure 2-4: Operational Flowchart Tundra Semiconductor Corporation MEMORY¥MEMORY TRANSFER External EOP N EOP F/F Setting READY External EOP N EOP F/F Setting READY Internal External EOP N Y HLDA N Tundra Semiconductor Corporation ...
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... HRQ Valid from CLK HIGH Delay Time DQ1 t HRQ Valid from CLK HIGH Delay Time DQ2 t LOW from CLK LOW Setup Time EOP EPS t Pulse Width EOP EPW Tundra Semiconductor Corporation = - Limits (5 MHz) Min ) Delay Time - 1 ) Delay Time - ...
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... Tundra Semiconductor Corporation = Limits (8 MHz) Limits (10 MHz) Max Min Max Min Max 110 - 90 - 150 - 90 - 110 - Tundra Semiconductor Corporation Cont'd Units ...
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... S S IDLE IDLE 0 CLK t QS DREQ t DQ1 HRQ t HS HLDA AEN ADSTB DB 0-7 A 0-7 DACK IOR, MEMR IOW, MEMW INT EOP EXT EOP Tundra Semiconductor Corporation AEL t STT t STL t ASS t t AHS FADB t AFDB t FAAB ADDRESS VALID t ...
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... ADDRESS VALID t AFDB A IN 8-15 t FADB t DCL t t IDH DCTR t IDS t EPS Tundra Semiconductor Corporation STT t AHS ADDRESS VALID t AFDB A OUT 8- ODH ODV t DCTW t t DCL DCL (EXTENDED WRITE EPW Tundra Semiconductor Corporation S IDLE t AFAB t AFC t AFC ...
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... Tundra Semiconductor Corporation c) Compressed Transfer Timing CLK A 0-7 IOR, MEMR IOW, MEMW READY INT EOP EXT EOP Tundra Semiconductor Corporation ASM t t DCTR DCL t DCTW EPS t EPW CA82C37A ASM t t DCTR DCL t DCTW ...
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... CA82C37A d) Ready Timing CLK IOR, MEMR IOW, MEMW READY e) Reset Timing V DD RESET IOR, IOW 2- DCL t t DCL DCL RSTD t RSTW Tundra Semiconductor Corporation DCTR t DCTW RSTS Tundra Semiconductor Corporation ...
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... RW t ADR from HIGH Hold Time WRITE HIGH from WRITE WC t Data from HIGH Hold Time WRITE WD t Width WRITE WWS Tundra Semiconductor Corporation = - Limits (5 MHz) Min LOW 10 READ 130 130 130 HIGH 0 READ - HIGH 0 500 2•t ...
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... AR IOR Slave Mode Write Timing CS IOW 2-30 ADDRESS MUST BE VALID RDE WWS t AW INPUT VALID t DW INPUT VALID Tundra Semiconductor Corporation RDF DATA OUT VALID Tundra Semiconductor Corporation ...
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... Tundra Semiconductor Corporation OUTPUT FROM DEVICE UNDER TEST All Outputs Except EOP INPUT +0 1 -0.4 V OUTPUT 2.0 V 0.8 V Tundra Semiconductor Corporation Includes stray and jig capacitance Pins V 1 1.7 V EOP VDD Figure 2-7: AC Test Circuits OUTPUT ...
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... and EOP 3-0 , RESET and DREQ CS 3-0 Tundra Semiconductor Corporation =+5 V 10%, V =0V Limits Min Max 2 -1.0 +1 -10.0 +10 0.3 DD -0.3 0.8 2 0.3 DD -0.3 0.7 - 0.4 2.4 - VDD - 0 0.4 - 100 ns ns. CY Tundra Semiconductor Corporation Units mA/ mHz ...
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... Note: Stresses beyond those listed above may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Tundra Semiconductor Corporation = V = 0V, V ...
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... Compressed timing X If bit Fixed priority 1 Rotating priority 0 Late write selection 1 Extended write selection X If bit DREQ sense active HIGH 1 DREQ sense active LOW 0 DACK sense active LOW 1 DACK sense active HIGH . EOP be prevented from incrementing Tundra Semiconductor Corporation or ...
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... Channel 2 mask bit cleared 1 Channel 2 mask bit set 0 Channel 3 mask bit cleared 1 Channel 3 mask bit set Not used Figure 2-10: Mask Register (Write Operation) Tundra Semiconductor Corporation not Auto- EOP Figure 2-11: Mask Register (Set/Reset Mode Register Each of the channels has a 6-bit mode register associated with it ...
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... The Temporary Register is used to hold data during memory- to-memory transfers. When the transfers are completed, the last word moved can be read by the microprocessor. Note that the Temporary Register always contains the last byte transferred in the previous memory-to-memory operation, unless cleared by a Reset or Master Clear. Tundra Semiconductor Corporation ...
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... The active cycle is com- posed of several internal states, depending on the options that have been selected and the type of operation that has been requested. Tundra Semiconductor Corporation OPERATIONAL DESCRIPTION When performing I/O-to-memory or memory-to-I/O DMA the CA82C37A can enter seven distinct states, each com- posed of one full clock period ...
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... The CA82C37A will respond to DREQ and generate DACK but all other outputs except HRQ will be disabled. An exter- nal EOP will be ignored by the initial device, but will have pulse. the usual effect on the added device. Tundra Semiconductor Corporation ) is EOP is encountered, or EOP Tundra Semiconductor Corporation ...
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... Word count register decremented by 1 Address register incremented (or decremented I/O memory transfers, data is transferred directly without being handled by the CA82C37A. Tundra Semiconductor Corporation When programming cascaded controllers, start with the first level device (the one closest to the microprocessor). After Reset, the DACK outputs are programmed to be active low and are held in the high state ...
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... Thus any one channel is prevented from monopo- lizing the system. Note that regardless of which priority scheme is chosen, pri- ority is evaluated every time a HLDA is returned to the CA82C37A. Tundra Semiconductor Corporation signals during EOP Rotating CH CH ...
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... Tundra Semiconductor Corporation During Block and Demand Transfer mode service, which include multiple transfers, the addresses generated will be sequential. For many transfers the data held in the external address latch will remain the same. This data need only change when a carry or borrow from A the normal sequence of addresses ...
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... Read order is channel 0 first, channel 3 last. The lower two bits on all Mode Registers will read as ones Tundra Semiconductor Corporation IOR IOW Tundra Semiconductor Corporation ...
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... Current Word Count Base and Current Address Current Address 2 Base and Current Word Count Current Word Count Base and Current Address Current Address 3 Base and Current Word Count Current Word Count Tundra Semiconductor Corporation Signals Operation CS IOR IOW Write ...
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... V DD MEMR V DD Tundra Semiconductor Corporation and (or and ) being active. IOR MEMW MEMR IOW CA82C37A CLK EOP CS STB ADSTB HLDA OE AEN IOR IOW MEMR MEMW 82C82 HRQ DREQ DACK ADDRESS BUS CS DREQ I/O DEVICE DATA BUS Tundra Semiconductor Corporation V DD IOR IOW ...
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... Figure 2-1: PLCC Pin Configurations Tundra Semiconductor Corporation CMOS SERIAL CONTROLLER INTERFACE The Tundra CA82C52 is a high performance, single chip programmable Transmitter (UART) and Baud Rate Generator (BRG). The Baud Rate Generator can be programmed for one of 72 different baud rates using a single industry standard crystal or external frequency source ...
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... CONTROL & STATUS REGISTERS TRANSMITTER BUFFER REGISTER RECEIVER BUFFER REGISTER MODEM CONTROL & STATUS REGISTERS INTERNAL DATA BUS Figure 2-3: CA82C52 Block Diagram Tundra Semiconductor Corporation TBRE DR TRANSMITTER REGISTER SDO P S RECEIVER SDI REGISTER P S CTS DSR DTR RTS Tundra Semiconductor Corporation ...
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... RST Tundra Semiconductor Corporation Name and Function Address Inputs: The address lines select the various internal registers during CPU bus operations. Clock Out: This output is user programmable to provide either a buffered IX output or a buffered Baud Rate Generator (16x) clock output. The buffered IX (Crystal or external clock source) output is provided when the Baud Rate Select Register (BRSR) bit 7 is set to a zero ...
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... Write: The input causes data from the data bus (D WR CA82C52. Addressing and chip select action is the same as for read operations Tundra Semiconductor Corporation bit in the MCR or whenever a RTS is false, RST is true, when the CTS - input to the 0 7 Tundra Semiconductor Corporation ...
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... CPU to read their inputs. DSR . Tundra Semiconductor Corporation FUNCTIONAL DESCRIPTION The format of the data character being transmitted (eg: number of data bits, parity control and the number of stop bits) is controlled by the UART Control Register. Changes in the status of the device at any given time is reflected in the UART Status Register ...
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... Control Consists ns, whichever is 6 smaller Tundra Semiconductor Corporation = 0V) SS Limits (16 MHz) Units Min Max 0 16 MHz 190 150 120 Tundra Semiconductor Corporation ...
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... OUT _____ CSO WRITE ___ OPERATION ___ RD READ OPERATION Tundra Semiconductor Corporation = Test Conditions FREQ = 1 MHz Unmeasured pins returned to V SELECT VALID t SVCTL t CTLCTH t DVWH VALID t SVCTL t CTLCTH t RLDV VALID ...
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... OUTPUT FROM 1.7 V 520 Figure 2-6: AC Test Circuits PROPAGATION DELAY ENABLE/DISABLE DELAY - 0.4 V and and TF must Figure 2-7: AC Testing I/O Waveform Tundra Semiconductor Corporation TEST POINT 100 OUTPUT 90% 10% 15 ns. Tundra Semiconductor Corporation ...
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... Output Low Voltage OL Note typically 1 ma/MHz DD Note 2: Applies to data bus pins ( Note 3: Applies to pins , , Tundra Semiconductor Corporation = - Test Conditions must be 62.5 ns CHCL CLCH External Clock F = 2.45576 MHz ...
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... Exposure to maximum rating conditions for extended periods may affect device reliability. 2-54 Tundra Semiconductor Corporation +4 +5.5 V Commercial +70 C Industrial - +85 C -. +150 -10 +10.0 mA 300 C Tundra Semiconductor Corporation ...
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... Tundra Semiconductor Corporation PROGRAMMING INSTRUCTIONS Control Words The complete functional definition of the CA82C52 is programmed by the systems software. A set of control words (UCR, BRSR and MCR) must be sent out by the CPU to initialize the CA82C52 to support the desired communication format. These control words will program the character length, number of stop bits, even/odd/no parity, baud rate etc ...
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... Tx and Rx Odd 010 = Tx Even, Rx Odd 011 = Tx Odd, Rx Even 100 = Tx Even, Rx check disabled 101 = Tx Odd, Rx check disabled 11X = Generation, check disabled bits bits bits bits Set to 00 for future product upgrade compatability Tundra Semiconductor Corporation ...
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... Generator output (16x baud rate clock) is output on the CO output. The Baud Rate Generator output is always a 50% nominal duty cycle except when external is selected and the Prescaler is set Tundra Semiconductor Corporation PRESCALER SELECT DIVISOR ...
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... Table 2-9: Baud Rate% Error Baud Rate Actual 2000 1986.2 134.5 133.33 110 109.71 Tundra Semiconductor Corporation and outputs are directly RTS DTR 2 4 16/3 8 32 128 192 256 288 352 512 768 Percent Error 0.69% 0.87% 0.26% Tundra Semiconductor Corporation ...
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... CA82C52 operation See Modem Status Register description for a description of register flag images with respect to output pins. Tundra Semiconductor Corporation REQUEST TO SEND (RTS) DATA TERMINAL READY (DTR) ...
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... CA82C52 SERIAL DATA FROM TRANSMITTER REGISTER ECHO MODE SERIAL DATA TO RECEIVER REGISTER Figure 2-11: LOOP and ECHO Mode Functionality 2-60 Tundra Semiconductor Corporation LOOP MODE Tundra Semiconductor Corporation SDO PIN 15 SDI PIN 25 ...
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... DR and TBRE output pins single interrupt for any status change in the CA82C52 is desired this can be accomplished by 'ORing' DR, TBRE and INTR together. Reading the USR clears all of the status bits in the USR register but does not affect associated output pins. Tundra Semiconductor Corporation CA82C52 or ) ...
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... TRANSMITTER BUFFER REGISTER EMPTY (TBRE) DATA READY (DR) Figure 2-12: USR Tundra Semiconductor Corporation Error 1 = Error Error 1 = Error Error 1 = Error Break 1 = Break status change 1 = Status change 0 = Not complete 1 = Complete 0 = Not Empty 1 = Empty 0 = Not Ready 1 = Ready Tundra Semiconductor Corporation ...
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... Tundra Semiconductor Corporation Note:The LSB, Bit 0 is the first serial data bit received. Tundra Semiconductor Corporation CLEAR TO SEND (CTS) DATA SET READY (DSR Undefined Figure 2-13: MSR ...
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... CPU to read. Failure to read the data in the RBR before complete reception of the next character can result in the loss of the data in the Receiver Register. The OE flag in the USR register indicates the overrun condition. 2-64 Tundra Semiconductor Corporation ). Bit data word is always the first data bit received. The 0 0 Tundra Semiconductor Corporation ...
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... The TBRE output pin and flag (USR register) reflect the status of the TBR. The TC flag (USR register) indicates when both the TBR and TR are empty Note:The LSB, Bit 0 is the first serial data bit transmitted. Tundra Semiconductor Corporation Bit 0 Bit 1 Bit 2 Bit 3 ...
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... POSITIVE ___ ___ OR NEGATIVE DSR, CTS (MSR) EDGE DETECT __ RD (MSR) 2-66 INTERRUPT STRUCTURE ) will trigger the edge detection circuitry with any change of status. Reading the MSR MIEN (MCR) Figure 2-16: Interrupt Structure Tundra Semiconductor Corporation INTR PIN 24 INTEN (MCR) Tundra Semiconductor Corporation ...
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... This is due to the sinusoidal nature of the drive circuitry when using a crystal. GND * for for Tundra Semiconductor Corporation Table 2-10: Crystal Specifications Parameter Frequency Type of Operation Load Capacitance (CL) R series (Max ...
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... OR _____ (MAX MODE) IOWR IR X INT INT ____ ____ INTA INTA CLK CA82C59A 5 MHz 2.5 MHz 15 MHz Figure 2-18: 80C86/CA82C52 Interface Tundra Semiconductor Corporation ____ CSO SDO __ RD SERIAL DATA ___ 82C52 WR SDI 3 INTR, DR, TBRE IX Tundra Semiconductor Corporation ...
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... CLK0 Figure 2-1: PLCC Pin Configurations Tundra Semiconductor Corporation PROGRAMMABLE INTERVAL TIMER The CA82C54 is a counter/timer device that includes complete pin and functional compatibility with the industry standard 8254. Designed for fast 10 MHz operation, it has three independently programmable 16 bit counters and six programmable counter modes ...
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... CA82C54 - BUFFER CONTROL WORD REGISTER 2-70 DATA BUS READ/ WRITE LOGIC 8 Figure 2-3: CA82C54 Block Diagram Tundra Semiconductor Corporation CLK 0 GATE0 COUNTER 0 OUT 0 CLK 1 COUNTER GATE1 1 OUT1 CLK 2 COUNTER GATE2 2 OUT 2 Tundra Semiconductor Corporation ...
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... VDD 14 12 VSS Tundra Semiconductor Corporation Type Name and Function Address: These two address pins are used to select the Control Word Register (for read or write operations), or one of the three Counters. They are normally connected to the system address bus ...
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... CR transferring both bytes simultaneously from CR. Note that CR is the interface between CE and the data bus, since CE cannot be accessed directly. Tundra Semiconductor Corporation and OL ) provide followed time and CR ) behave otherwise loaded by L Tundra Semiconductor Corporation M ...
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... STATUS CONTROL LATCH WORD REGISTER STATUS REGISTER CONTROL LOGIC GATEn CLKn OUTn Tundra Semiconductor Corporation 8-BIT INTERNAL BUS (16-BIT DOWN COUNTER Figure 2-4: Block Diagram of a Counter CA82C54 ...
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... Tundra Semiconductor Corporation Units ...
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... Tundra Semiconductor Corporation Figure 2-5: Timing Diagrams a) Write Timing DATA BUS WR b) Read Timing A 0 DATA BUS Tundra Semiconductor Corporation VALID VALID CA82C54 2-75 ...
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... ODG t WO 2.0 2.0 TEST POINTS 0.8 0.8 Figure 2-6: AC Testing I/O Waveform DEVICE UNDER TEST C = 150 includes jig capacitance L Figure 2-7: AC Testing Loading Circuit Tundra Semiconductor Corporation Last byte of count being written 150 Tundra Semiconductor Corporation ...
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... Output Low Voltage OL Table 2-4: Capacitance ( Symbol Parameter C I/O Capacitance I/O C Input Capacitance IN C Output Capacitance OUT Tundra Semiconductor Corporation = - + 10 Test Conditions CLK Freq = 5 MHz, CA82C54-5 CLK Freq = 8 MHz, CA82C54-8 CLK Freq = 10 MHz, CA82C54- ...
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... Exposure to maximum rating conditions for extended periods may affect device reliability. 2-78 Tundra Semiconductor Corporation +4 +5.5 V Commercial +70 C Industrial - +85 C -. +150 -10 +10.0 mA 300 C Tundra Semiconductor Corporation ...
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... SC1 SC0 RW1 RW0 SELECT COUNTER SELECT COUNTER SELECT COUNTER READ - BACK COMMAND (see READ OPERATIONS) Tundra Semiconductor Corporation PROGRAMMING BCD BINARY COUNTER 16 - BITS 0 BINARY CODED DECIMAL (BCD) ...
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... MSB of count-Counter inputs. The only requirement is that the CLK input Tundra Semiconductor Corporation , A inputs), and each Tundra Semiconductor Corporation ...
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... SC1, SC0 - specify counter to be latched designates Counter Latch Command don't care Note: Don't care bits (X) should insure compatibility with future Newbridge Microsystem products Tundra Semiconductor Corporation SC1 SC0 COUNTER 0 ...
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... Latch count of selected counter( Latch status of selected counter( Selected Counter Selected Counter Selected Counter 1 Figure 2-10: Read-Back Command Format Tundra Semiconductor Corporation 4 contain the counter's programmed Mode exactly Tundra Semiconductor Corporation = 0 and (STATUS ...
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... D 6 NULL OUTPUT COUNT OUT PIN OUT PIN Notes: Tundra Semiconductor Corporation RW1 RW0 M2 COUNTER PROGRAMMED MODE (see Figure 2-8) NULL COUNT COUNT AVAILABLE FOR READING Figure 2-11: Status Byte Table 2-8: Null Count Operation This Action: 1 ...
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... Counter 1 Tundra Semiconductor Corporation Command Word Tundra Semiconductor Corporation ...
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... Tundra Semiconductor Corporation Counter: New counts are loaded, with the largest possible initial count being zero (0), equivalent to 2 counting and 10 Counters decremented on the falling edge of CLK do not stop when they reach zero. In Modes and 5 the ...
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... Tundra Semiconductor Corporation Rising - •Enables counting •Initiates counting •Resets output after next clock •Initiates counting •Enables counting •Initiates counting •Enables counting - •Enables counting •Initiates counting Tundra Semiconductor Corporation High - - ...
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... If an initial count is written while GATE = 0, it will still be loaded on the next CLK pulse. When GATE goes high, OUT will go high N CLK pulses later. A CLK pulse is not required to load the Counter as this has already been done. Tundra Semiconductor Corporation MODE DEFINITIONS LSB = 4 ...
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... Tundra Semiconductor Corporation LSB = LSB = LSB = 4 LSB = Figure 2-14: Mode 2 Timing Tundra Semiconductor Corporation ...
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... OUT goes high again and the Counter is reloaded with the initial count minus one. The above pro- cess is repeated indefinitely. So for odd counts, OUT is high for (N + 1)/2 counts and low for (N - 1)/2 counts. Tundra Semiconductor Corporation LSB = 4 WR ...
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... FF Tundra Semiconductor Corporation LSB = LSB = LSB = 2 LSB = Figure 2-17: Mode 5 Timing Tundra Semiconductor Corporation ...
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... I/O ports together with TTL compatibil- ity over the full temperature range eliminates the need for pull-up resistors. The CA82C55A is a general purpose programmable I/O de- vice designed for use with several different microprocessors. Its high speed and high performance make it ideally suited for ...
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... DATA BUS DATA BUS 7 0 BUFFER RD READ/ WR WRITE A CONTROL 1 LOGIC A 0 RESET CS 2-92 GROUP A CONTROL 8-BIT INTERNAL DATA BUS GROUP B CONTROL Figure 2-3: CA82C55A Block Diagram Tundra Semiconductor Corporation GROUP I PORT (8) GROUP I/O A PORT UPPER (4) GROUP B I PORT LOWER ...
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... Chip Select: A low on this input enables the CA82C55A to respond to and are ignored otherwise Data Bus: Bi-directional, tri-state data bus lines, connected to system data bus. Port A, Pins 0-7: An 8-bit data output latch/buffer and an 8-bit data input buffer. Port B, Pins 0-7: An 8-bit data output latch/buffer and an 8-bit data input buffer. ...
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... FUNCTIONAL DESCRIPTION Ports A, B and C The CA82C55A contains three 8-bit ports (A, B and C). All can be configured in a wide variety of functional characteris- tics by the system software, but each also has its own special features. Port A: One 8-bit data output latch/buffer and one 8-bit input latch ...
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... CA82C55A Units 125 ns 100 ns ns 100 175 120 ns 160 ...
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... CA82C55A Figure 2-5: Timing Diagrams a) Mode 0 (Basic Input) RD INPUT Mode 0 (Basic Output CS OUTPUT 2- Tundra Semiconductor Corporation Tundra Semiconductor Corporation ...
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... Tundra Semiconductor Corporation c) Mode 1 (Strobed Input) STB IBF INTR RD INPUT FROM PERIPHERAL d) Mode 1(Strobed Output) WR OBF INTR ACK OUTPUT Tundra Semiconductor Corporation SIB t SIT WOB t WIT t WB CA82C55A t RIB t RIT t AOB AIT 2-97 ...
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... CA82C55A e) Mode 2 (Bi-directional) WR OBF INTR ACK STB IBF PERIPHERAL BUS RD Note: Any sequence where WR • + • • STB RD OBF MASK f) Write Timing DATA BUS WR 2-98 t WOB SIB occurs before , and occurs before ACK STB • ). ACK ...
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... Tundra Semiconductor Corporation HIGH IMPEDANCE 2.0 2.0 TEST POINTS 0.8 0.8 Figure 2-6: AC Testing I/O Waveform DEVICE UNDER TEST C = 150 set at various voltages during testing to guarantee EXT includes jig capacitance. L Figure 2-7: AC Testing Load Circuit CA82C55A VALID HIGH IMPEDANCE C = 150 EXT 2-99 ...
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... CA82C55A Table 2-3: DC Characteristics (T Symbol Parameter I V Supply Current Input Leakage Current I OFL Output Float Leakage Current I PHH Port Hold High Leakage Current I PHL Port Hold Low Leakage Current V Input High Voltage IH V Input Low Voltage IL V Schmitt Trigger Input High Voltage ...
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... Exposure to maximum rating conditions for extended periods may affect device reliability. Tundra Semiconductor Corporation = Test Conditions FREQ = 1 MHz Unmeasured pins returned Commercial Industrial CA82C55A Min Max Units - +4 +5 + +85 C -. ...
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... OPERATIONAL DESCRIPTION the other modes may be deleted by using a single output in- struction. This allows a single CA82C55A to service a variety of peripheral devices with a simple software maintenance routine. The modes for Port A and Port B can be separately defined, while Port C is divided into two portions as required by the Port A and Port B definitions ...
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... Figure 2-9: Mode Definitions and Bus Interface Tundra Semiconductor Corporation ADDRESS BUS CONTROL BUS DATA BUS I/O I I/O CONTROL CONTROL 0 OR I/O OR I/O C I/O I/O 0 CONTROL I BI-DIRECTIONAL - CA82C55A 2-103 ...
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... Bit Set/Reset opera- tion as if they were data output ports. Interrupt Control Functions When the CA82C55A is operating in Mode 1 or Mode 2, con- trol signals are provided for use as interrupt request inputs to the CPU. The interrupt request signals, generated from Port C, ...
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... Refer to Figure 2-11 for an example of a Mode 0 Configura- tion Tundra Semiconductor Corporation CA82C55A C Figure 2-11: Mode 0 Configuration CA82C55A - 2-105 ...
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... CA82C55A Table 2-7: Mode 0 Port Definition Control Word Bits Control Group A Word # ...
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... ACK (Acknowledge Input): A LOW on this input informs the ACK CA82C55A that the data from Port A or Port B has been ac- cepted. (i.e. a response from the peripheral device indicating that it has received the data output by the CPU). INTR (Interrupt Request): A HIGH on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU ...
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... CA82C55A CONTROL WORD CONTROL WORD 2-108 1 INPUT 0 = OUTPUT Figure 2-12: Mode 1 Input Tundra Semiconductor Corporation MODE 1 (PORT INTE PC STB ...
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... PC 4 INPUT 0 = OUTPUT Figure 2-13: Mode 1 Output MODE 1 (PORT OBF 7 INTE PC ACK INTR I/O 4,5 MODE 1 (PORT OBF 1 INTE PC ACK INTR 0 CA82C55A 2-109 ...
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... CA82C55A Mode 2 (Strobed Bi-directional Bus I/O) This mode provides a means for communicating with a pe- ripheral device or a structure on a single 8-bit bus to facilitate both the transmitting and the receiving of data (bi-directional bus I/O). Handshaking signals maintain prop- er bus flow discipline in a similar manner to Mode 1. Inter- rupt generation and enable/disable functions are also available ...
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... PC STB IBF INTR I/O 6 OBF B PC ACK INTR OBF A PC ACK INTR I/O 4 STB IBF INTR 0 B PORT B - STROBED INPUT CA82C55A 2-111 ...
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... CA82C55A MODE 2 AND MODE 0 (INPUT) CONTROL WORD 1 2 INPUT 0 = OUTPUT RD WR MODE 2 AND MODE 1 (OUTPUT) CONTROL WORD ...
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... INTR IBF IBF OBF STB B ACK B STB B INTR INTR INTR I/O STB A STB A IBF IBF I I/O I/O ACK A I/O I/O OBF A CA82C55A MODE 2 All BI-DIRECTIONAL Not Used in MODE 2 INTR I/O B I/O OBF B I/O ACK B INTR INTR A A I/O STB A I/O OBF A ACK A ACK A OBF OBF A A 2-113 ...
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... Reading Port C Status In Mode 0, Port C transfers data to or from the peripheral device. When the CA82C55A is in Modes Port C generates or accepts handshaking signals with the peripheral device. Reading Port C allows the programmer to test or verify the status of each peripheral device and change the program flow accordingly ...
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... Mode 1 or Mode 2) STB (Output Mode 1 or Mode 2) ACK A 6 (Defined by Mode 0 or Mode 1 Selection INTE IBF INTE INTR GROUP A Alternate Port C Pin Signal (Mode) (Input Mode 1) STB B CA82C55A GROUP B 2-115 ...
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... By examining the interface characteristics of the I/O device for both data transfer and timing, and matching this information to the examples and tables in the Operational Description, a control word can easily be developed to initialize the CA82C55A to exactly fit the application. Figure 2-20 to Figure 2-26 il- lustrate a few examples of typical CA82C55A applications. ...
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... CA82C55A FULLY R 2 DECODED R KEYBOARD SHIFT CONTROL STROBE ACK BURROUGHS 2 SELF-SCAN B 3 DISPLAY BACKSPACE CLEAR ...
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... CA82C55A INTERRUPT REQUEST PC 3 MODE 1 (INPUT) CA82C55A MODE 0 (INPUT) INTERRUPT REQUEST Figure 2-22: Keyboard and Terminal Address Interface 2-118 SHIFT 6 CONTROL STROBE 4 ACK PC 5 BUSY TEST ...
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... MODE (INPUT Figure 2-23: Digital to Analog, Analog to Digital Tundra Semiconductor Corporation LSB 12-BIT D-A CONVERTER (DAC) MSB STB DATA OUTPUT EN SAMPLE EN STB LSB 8-BIT A-D CONVERTER (ADC) MSB CA82C55A ANALOG OUTPUT ANALOG INPUT 2-119 ...
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... CA82C55A INTERRUPT REQUEST PC MODE 2 CA82C55A MODE 0 (OUTPUT) 2-120 Figure 2-24: Basic CRT Controller Interface Tundra Semiconductor Corporation FLOPPY DISK ...
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... Figure 2-25: Basic Floppy Disk Interface CRT CONTROLLER R 2 • CHARACTER GEN. R • REFRESH BUFFER 3 • CURSOR R 4 CONTROL R 5 SHIFT CONTROL DATA READY ACK BLANKED BLACK/WHITE ROW STB COLUMN STB CURSOR H/V STB CURSOR/ROW/COLUMN ADDRESS H & V CA82C55A 2-121 ...
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... CA82C55A INTERRUPT REQUEST PC 3 MODE 1 (INPUT) CA82C55A MODE 0 (INPUT) MODE 0 (OUTPUT) Figure 2-26: Machine Tool Controller Interface 2-122 ____ PC STB 4 ____ PC ACK 5 PC STOP/ START/STOP 0 PC LIMIT SENSOR (H/ ...
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... Figure 2-1: PLCC Pin Configurations Tundra Semiconductor Corporation PROGRAMMABLE INTERRUPT CONTROLLER The Tundra CA82C59A is a high performance, completely programmable interrupt controller. It can process eight inter- rupt request inputs, assigning a priority level to each one, and is cascadable interrupt requests. Individual interrupt- ing sources are maskable ...
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... INTA CONTROL LOGIC IN- SERVICE REGISTER (ISR) INTERRUPT MASK REGISTER (IMR) DATA and CONTROL LOGIC INTERRUPT LOGIC Figure 2-3: CA82C59A Block Diagram Tundra Semiconductor Corporation INT INTERRUPT PRIORITY REQUEST RESOLVER REGISTER (IRR) Tundra Semiconductor Corporation ...
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... Tundra Semiconductor Corporation Name and Function It is used by the CA82C59A to decipher various command words written by the CPU, and Status information read by the CPU typically connected to the CPU - A address line. Cascade Line: These signals are outputs for the master CA82C59A, and inputs for slaved CA82C59As ...
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... The actual operation of the CA82C59A and its many modes are described in the section following device specifications and characteristics. Tundra Semiconductor Corporation ) connecting master and slave are handled by the 0 7 Tundra Semiconductor Corporation ...
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... WR WLWH Notes: 1. The time to move to/from command (read/write). INTA 2. The time to clear the input latch in edge-triggered mode. 3. The time to move from read to write operation. 4. The time to move to the next Tundra Semiconductor Corporation = - Test Conditions Note ...
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... Note that IR input should remain at a high level until the leading edge of the first INTA pulse. 2-128 t JHIH t JLJH t IAIAL CALL (0CDH) t CVIAL t CVDV t IALCV t JHIH t JLJH t IAIAL t CVIAL t CVDV t IALCV Tundra Semiconductor Corporation t RHDZ t RLDV ADDR ADDR LOW HIGH t RHDZ t RLDV VECTOR NUMBER Tundra Semiconductor Corporation ...
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... Tundra Semiconductor Corporation c) Read Cycle , Write Cycle , Tundra Semiconductor Corporation t AHRL t RLRH t RLDV t AHDV t AHWL t WLWH t DVWH CA82C59A t RHAX t RHDZ t WHAX t WHDX 2-129 ...
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... AC Testing: All input signals must switch between V fall times must be 15 ns. All timing measurements are made at 2.4V and 0.45V. 2-130 t RHEH t RLEL t RHRL t RV1 t RV1 t IAIAH t RV2 t CHCL OUTPUT IL Figure 2-5: AC Testing I/O Waveforms Tundra Semiconductor Corporation t RV1 t WHWL 2.4V 0.45V - 0.4V and V + 0.4V. Input rise and IH Tundra Semiconductor Corporation ...
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... HY V Output HIGH voltage OH V Output LOW voltage OL Note 1: Applies to pins IR - Note 2: Applies to pins , , Tundra Semiconductor Corporation Note V1 1. 4.5V TEST POINT *Includes stray and jig capacitance Figure 2-6: AC Testing Load Circuit = - Test Conditions 0v VIN VDD ...
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... IN SS Test Conditions FREQ = 1 MHz Unmeasured pins returned Commercial Industrial Tundra Semiconductor Corporation Min Max Units - +4 +5 + +85 C -. +150 -10 +10.0 mA 300 C Tundra Semiconductor Corporation ...
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... Automatic EOI mode, where the ISR bit is reset automatically at the end of the third . INTA Tundra Semiconductor Corporation OPERATIONAL DESCRIPTION Vector Mode In VECTOR mode, the interrupt service routine address is calculated by the CPU from a one byte interrupt vector supplied by the CA82C59A. The significant bits T interrupt vectors are loaded into the CA82C59A during the initialization procedures ...
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... TO DATA BUS OUTPUT ADDRESS HIGHER BYTE ( DATA BUS SET BIT n OF ISR RESET BIT n OF IRR RESET BIT n OF ISR Tundra Semiconductor Corporation CPU (INTERRUPT ENABLE) GENERATE FIRST INTA PULSE WHEN INT IS RECEIVED SAVE OPCODE (OCDH) GENERATE SECOND INTA PULSE SAVE AD ...
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... CA82C59A When the Interval = 8, bits A are programmed, with A CONTENTS OF SECOND INTERRUPT VECTOR BYTE During the third enabled onto the bus. This address was initially programmed as byte 2 of the initialization sequence (A Tundra Semiconductor Corporation CONTENTS OF FIRST INTERRUPT VECTOR BYTE ...
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... PULSE WHEN INT IS RECEIVED SAVE OPCODE (OCDH) - CAS 2 0 GENERATE SECOND INTA PULSE SAVE AD GENERATE THIRD INTA PULSE SAVE AD IRR USE AD TO EXECUTE INTERRUPT ROUTINE ISSUE EOI COMMAND TO IRm OF SLAVE ISSUE EOI COMMAND FOR IRm Tundra Semiconductor Corporation L H AND ...
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... GENERATED INTERRUPT REQUEST IRn HOLD IRn HIGH UNTIL FIRST INTA PULSE IS GENERATED RESET INTERRUPT REQUEST AT IRn SEQUENCE Figure 2-10: Vector Mode Operation (Single CA82C59A Systems) Tundra Semiconductor Corporation CA82C59A SET BIT n OF IRR IS IRn HIGHEST PRIORITY? YES GENERATE INT FOR IRn INTERNAL ...
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... INTA Figure 2-11: Vector Mode Address Byte Tundra Semiconductor Corporation Tundra Semiconductor Corporation ...
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... REQUEST AT IRm INTA SEQUENCE OUTPUT VECTOR TO DATA BUS SET BIT m OF ISR RESET BIT m OF RESET BIT m OF ISR Figure 2-12: Vector Mode Operation (Cascaded CA82C59A Systems) Tundra Semiconductor Corporation MASTER CA82C59A (n) m SNGL = 0) (ICW 1 SET BIT n OF IRR IS IRn NO HIGHEST PRIORITY? ...
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... Write Words for ICW 3 Write writing procedure 4 Write After initialization 1 Tundra Semiconductor Corporation Function Bit Programming ICW Tundra Semiconductor Corporation ...
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... ICW 1 programmed. • bit of ICW = 0, then functions selected in ICW 4 1 are reset: Non-buffered Mode, no Automatic EOI, Call Mode operation. • then CA82C59A will expect ICW 4 Tundra Semiconductor Corporation PROGRAMMING Bit Definitions (ICW IC 4 SNGL ADI LTIM A 5-15 A 11-15 must ...
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... ICW is set. Note that for Tundra Semiconductor Corporation ICW 1 ICW 2 IS IRn NO (SNGL = 1) HIGHEST PRIORITY? YES (SNGL = 0) ICW 3 IS IRn NO ( HIGHEST PRIORITY? YES ( ICW 4 READY TO ACCEPT INTERRUPT REQUESTS Figure 2-13: Initialization Flow Chart Tundra Semiconductor Corporation ...
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... R This bit determines if interrupt priority rotation is in effect indicates priorities will be ro- tated, perhaps combined with other modes. Tundra Semiconductor Corporation Bit Definitions (OCW OCW is used to program the Special Mask Mode, the Polling 3 Mode, and select internal registers to be read by the CPU. ...
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... NOTE THAT THE SLAVE EQUAL TO THE 5 CORRESPONDING MASTER IR INPUT 6 7 INTERRUPT 1 VECTOR MODE MODE 0 CALL MODE SELECT END OF 1 AUTO EOI INTERRUPT 0 NORMAL EOI MODE BUFFER MODE SELECT 1 SPECIAL FULLY NESTED MODE 0 NOT SPECIAL FULLY NESTED MODE Tundra Semiconductor Corporation ...
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... OCW PRIORITY ROTATION * 0 AND * 1 EOI COMMAND ARE USED OCW Figure 2-15: Operational Command Word Format Tundra Semiconductor Corporation ...
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... SNGL bit of ICW is set to 1). M signal only in Vector mode). At the INTA bus lines are normally held in a LOW state, and 0-2 signal (either second INTA ) of the master de- 0-7 ) input of each CA82C59A in the system. Tundra Semiconductor Corporation 0 in its initial ), enabling 0-2 sig- INTA ...
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... The EOI mode selected depends on the nesting mode currently programmed. The options are dis- cussed in the sections following. Tundra Semiconductor Corporation Automatic EOI (AEOI) Mode In AEOI Mode, the ISR bit corresponding to the interrupt is set and reset automatically during the final means that the CPU does not have to issue an EOI command at the end of the interrupt routine ...
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... IMR IMR IMR IMR IMR IMR Set Special Mask Mode SSMM = 1 AND SMM = the highest pri- 0 the lowest. 7 Tundra Semiconductor Corporation ISR ISR, IMR ISR ...
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... IR 4 serviced. The HIGH level is maintained at IR Figure 2-19: Fully Nested Mode Tundra Semiconductor Corporation Special Fully Nested Mode This mode is very similar to the Fully Nested Mode, but is used in systems with cascaded CA82C59s preserve the interrupt priorities within each slave, as well as within the master ...
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... ISR ISR ISR ISR ISR ISR HIGHEST PRIORITY LOWEST PRIORITY Figure 2-21: Effect of Rotation Tundra Semiconductor Corporation with (Rotate on 2 ISR ISR HIGHEST PRIORITY ISR ISR ...
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... IR input goes LOW before this time, the interrupt will be registered as a default IR regardless of which IR input initi- 7 ated the interrupt request. This default IR tect (and subsequently ignore) spurious interrupt signals such as those caused by glitches or noise on the IR input lines. The technique is described below: Tundra Semiconductor Corporation ...
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... SET SET ISR CONTROL LOGIC NON-MASKED REQUEST INTERNAL DATA BUS NOTES: 1. MASTER CLEAR ACTIVE ONLY DURING ICW1 ________ 2. FREEZE IS ACTIVE ONLY _____ DURING INTA AND POLL SEQUENCES 3. D-LATCH TRUTH TABLE OPERATION D D FOLLOW HOLD n-1 Tundra Semiconductor Corporation ...
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... Tundra Semiconductor Corporation APPLICATION DIAGRAMS 16-BIT ADDRESS BUS CONTROL BUS 8-BIT DATA BUS CASCADE LINES SLAVE PROGRAM/ ENABLE BUFFER Figure 2-25: CA82C59A In Standard System Configuration Tundra Semiconductor Corporation I/ CAS 0 CAS 1 CAS 2 ___ ___ SP/ INTERRUPT REQUEST ...
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... MAXIMUM OF 64 INPUTS PER SYSTEM 3. TOTAL CAPACITY LIMITED BY CPU Figure 2-26: Multiple CA82C59As In A Cascaded System 2-154 CA82C59A SLAVE 1 CA82C59A SLAVE 8 CA82C59A SLAVE 1 CA82C59A SLAVE 1 CA82C59A SLAVE 2 CA82C59A SLAVE 8 MASTER IR INPUTS Tundra Semiconductor Corporation SYSTEM A SYSTEM B INTERRUPT REQUEST LINES SYSTEM n Tundra Semiconductor Corporation ...
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... SP/ (GND Figure 2-27: Multiple CA82C59A Masters In A Polled System Tundra Semiconductor Corporation 16-BIT ADDRESS BUS CONTROL BUS 8-BIT DATA BUS INT CS INTA CAS 0 CA82C59 SLAVE-B CAS 1 CAS 2 ___ ___ ...
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Product Index and Ordering 8000 Series Products Worldwide Sales Network Section ...
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...
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... Broken Arrow, OK 74013 Tel: 918-258-7723 Fax: 918-258-7653 Minnesota, North Dakota, South Dakota, Western Wisconsin Electromec Sales Inc. 1601 East Highway 13, Suite 102 Burnsville, MN 55337 Tel: 612-894-8200 Fax: 612-894-9352 Missouri, Southern Illinois, Iowa, Kansas, Nebraska Please contact Tundra Semiconductor directly at: 1-800-267-7231 Sales-159 ...
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... Erma Road Suite 201 San Diego, CA 92131 Tel: 619-549-5360 Fax: 619-549-5365 Oregon, Wahington State Electronic Sources, Inc. 6850 S.W. 105th, Suite B Beaverton, OR 97008 Tel: 503-627-0838 Fax: 503-627-0238 Electronic Sources, Inc. 1603 116th Ave. NE, Suite 115, Bellevue, WA 98004 Tel: 206-451-3500 Fax: 206-451-1038 Tundra Semiconductor Corporation ...
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... Fax 866763 Germany P I Electronic Engineering, GmbH Keitlanderstrasse 48 74354 Besegheim-Ottmarsheim, Germany Tel 4381 1153 Fax 4358 853 Hong Kong Please contact Tundra Semiconductor directly at: 613-592-0714 India Hynetic Electronics No. 50, 2nd Cross Gavipuram Extension, Bangalore, 560019, India Tel: 91-80-620852 Fax: 91-80-624073 ...
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... United Kingdom Welvar Electronics Ltd. MBM Box 66 Manor Lane, Rochester Kent, England ME5 1HS Tel 634 815033 Fax 634 832133 Thame Components Thame Park Road Thame, Oxfordshire 0X9 3UQ Tel 844 261188 Fax 844 261681 Tundra Semiconductor Corporation ...