IT8661F Integrated Technology Express, Inc., IT8661F Datasheet
IT8661F
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IT8661F Summary of contents
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... IT8661F & IT8661RF Plug and Play Super AT I/O Preliminary Specification V0.6 ...
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... All sales are subject to ITE’s Standard Terms and Conditions, a copy of which is included in the back of this document. ITE, IT8661F and IT8661RF are trademarks of ITE, Inc. Intel, Pentium, and MMX are claimed as trademarks by Intel Corp. Cyrix, M1, and SLiC/MP are claimed as trademarks by Cyrix Corp. ...
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... Features ................................................................................................................................................ 1 2. General Description.............................................................................................................................. 3 3. Pin Configuration ................................................................................................................................. 3 4. Block Diagram ...................................................................................................................................... 4 5. IT8661F and IT8661RF Pin Descriptions ............................................................................................. 5 6. Configuring Sequence Description ..................................................................................................... 9 6.1 General Description ......................................................................................................................... 9 6.2 MB PnP Mode ............................................................................................................................... 10 6.3 ISA PnP Mode ............................................................................................................................... 10 6.4 Plug and Play Operation Sequence ............................................................................................... 12 6.5 Description of the Configuration Registers ..................................................................................... 13 6.5.1 Logical Device Base Address.................................................................................................. 17 6 ...
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Serial Port 1 Configuration Registers (LDN=01h) ........................................................................... 21 6.8.1 Serial Port 1 Activate (Index=30h, Default=00h, ISA PnP/MB PnP) ........................................ 21 6.8.2 Serial Port 1 I/O Range Check (Index=31h, Default=00h, ISA PnP)........................................ 21 6.8.3 Serial Port 1 Base Address MSB ...
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IR Interrupt Type 2 (Index=73h, Default=02h, ISA PnP) (IT8661RF only) ........................... 25 6.11.11 IR DMA Channel Select 1 (Index=74h, Default=01h, ISA PnP/MB PnP) (IT8661RF only).... 25 6.11.12 IR DMA Channel Select 2 (Index=75h, Default=00h, ISA PnP/MB PnP) (IT8661RF only).... ...
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Data Transfer Commands Description .................................................................................... 36 7.3 Serial Channel Register Description............................................................................................... 49 7.3.1 Data Register.......................................................................................................................... 49 7.3.2 Control Registers: IER, IIR, FCR, DLL, DLM, LCR, MCR ........................................................ 49 7.3.3 Status Register LSR and MSR ................................................................................................ 51 7.3.4 Reset ...................................................................................................................................... ...
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Interrupt Request Timing ........................................................................................................ 88 9.6 EPP Address or DATA WRITE Cycle............................................................................................. 89 9.7 EPP Address or DATA READ Cycle .............................................................................................. 90 9.8 ECP Parallel Port Forward Timing Diagram ................................................................................... 91 9.9 ECP Parallel Port Backward Timing Diagram ................................................................................ ...
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Table 7-15. Description of the WRITE DELETED DATA Command............................................................. 43 Table 7-16. Description of the FORMAT A TRACK Command..................................................................... 44 Table 7-17. Description of the READ ID Command...................................................................................... 45 Table 7-18. Description of the RE-CALIBRATE Command .......................................................................... 45 Table 7-19. ...
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Table 9-14. Control Signal Delay Time of Parallel Port Timing .................................................................... 88 Table 9-15. Interrupt Request Timing of Parallel Port Timing....................................................................... 88 Table 9-16. EPP Address or DATA WRITE Cycle........................................................................................ 89 Table 9-17. EPP Address or DATA READ Cycle.......................................................................................... 91 ...
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... Standard mode -- bi-directional SPP - Enhanced mode – EPP V1.7 and EPP V1.9 compliant - High Speed mode -- ECP, IEEE1284 compliant - Backdrive current protection - Printer power-on damage protection IT8661F and IT8661RF Plug and Play Super AT I/O ITPA-PN-97014, W.B., Apr. 18, 1998 g Serial Ports - Base address 0x100h-0x0FF8h, seven (7) IRQ options ...
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... No N.V. memory is needed to store resource data for Plug and Play system applications. The IT8661F and IT8661RF consist of five (5) logical devices. One (1) high performance 2.88MB floppy disk controller, with digital data separator, supports two (2) 360K/ 720K/ 1.2M/ 1.44M/ 2.88M floppy disk drives. One multi- ...
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... DSKCHG# 18 XTALO 19 IRSOUT/GPIO10 20 XTALI 21 DRQ1 22 DACK1# DRQ0 23 24 IRQ5 25 IRQ10/GPIO11 26 IRQ11/GPIO12 27 A11 Note: IRSINH is available for IT8661RF only. IT8661F and IT8661RF IT8661F and IT8661RF 3 80 DSR1# 79 SOUT1 78 SIN1 77 AFD# 76 STB# 75 ERR# 74 SLIN# 73 INIT# 72 VCC 71 PD0 70 PD1 69 PD2 68 PD3 ...
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... Bus) FLOPPY DISK CONTROLLER INDEX# DENSEL#, XTALO TK00# MOTEA/B#, WPT# DRVA/B#, DIR# RDATA# STEP#, WDATA#, DSKCHG# WGATE# 4 IT8661F and IT8661RF PD0-PD7 MULTI-MODE BUSY, PE, PARALLEL SLCT, ACK#, PORT ERR# STB#, AFD#, INIT#, SLIN# SIN1, CTS1#, DSR1#, 16C550 RLSD1#, RI1# STANDARD COMPATIBLE ...
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... MHz or 48 MHz Crystal Oscillator Input. An external clock in use must be connected to this pin. DMA Request The logical devices of the IT8661F and IT8661RF can be mapped to individual DRQx via configuration register(0x74). These signals are cleared by the going-low of DACK and 3# signals. ...
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... General Purpose I/O. This pin is internally pulled up to 50K . 12-bit I/O Address bus Terminal Count, active high to indicate that data transfer is completed Interrupt Request The logical devices of the IT8661F and IT8661RF can be mapped to the individual IRQx via configuration register(0x70). Read Strobe, active low ...
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... Serial Port 1, Data Terminal Ready Output, active low. During the hardware reset, this pin and pin 81 become input and DTR1# is tristated, then latches the voltage level of MC0 to clarify systems that use the same IT8661F and IT8661RF I/O controller. (Refer to the general description of the configuring sequence on Page 9 ...
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... Infrared data input pin of 1-input FIR transceiver (IBM-like). The second function is General Purpose I/O. This pin is internally pulled up to 50K . The IT8661F is a high-frequency infrared data input pin of 2-input FIR transceiver(HP-like) or mode select output pin of 1-input FIR transceiver (IBM-like). The second function for both IT8661F and IT8661RF is General Purpose I/O ...
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... There are two configuration modes for IT8661F and IT8661RF, MB PnP mode and ISA PnP mode. The MC0 (pin 83) and MC1 (pin 81) are used to clarify different systems that use the same IT8661F and IT8661RF I/O controller. In ISA PnP mode, the latched values of MC0 and MC1 can be used as the serial number LSB of to clarify different systems that use the same IT8661F and IT8661RF I/O controller ...
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... MB PnP mode. Since the LDNs Data port are dynamic, users can assign logical devices 3F1h to be configured by ISA Plug and Play V1.0a 3BFh protocol because they always remain enabled 371h in PC resources. BE, 61 IT8661F and IT8661RF systems and thus utilize fixed ...
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... OR (WAKE<>CSN) STATE ACTIVE COMMANDS SET CSN RESET WAIT FOR KEY ISOLATION WAKE[CSN] SET RD-DATA PORT SERIAL ISOLATION Figure 6-2. PnP State Transition IT8661F and IT8661RF OR SET CSN=0 ACTIVE COMMAND NO ACTIVE COMMANDS INITIATION KEY (WAKE<>0) AND ACTIVE COMMANDS (WAKE=CSN) RESET WAIT FOR KEY WAKE[CSN] (WAKE< ...
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... The IT8661F and IT8661RF enter this state within 1.5ms after RESET signal or RESET command. The initiation key is written to IT8661F and IT8661RF. Each value of the initiation key is calculated after shifting the LFSR by one clock for each write, and the written data is compared with the calculated (expected) data. In this state, the chip will reset the LFSR to “ ...
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... MB PnP Chip ID Byte 1 MB PnP Chip ID Byte 2 MB PnP Chip Version/Multi-chips clarification MB PnP PnP Logical Device Enable Register MB PnP SOFTWARE SUSPEND/Input Clock Select Register MB PnP GPIO Function Enable Register[12:8] MB PnP GPIO Function Enable Register[7:0] 13 IT8661F and IT8661RF 0X0279h write-only 0X0A79h write-only ...
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... R/W 03h 02h 71h R 02h 02h F0h R/W 00h IT8661F and IT8661RF Access Mode Configuration Register or Action ISA PnP/MB PnP FDC Activate ISA PnP FDC I/O Range Check ISA PnP/MB PnP FDC Base Address MSB Register ISA PnP/MB PnP FDC Base Address LSB Register ...
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... R/W 01h 04h 75h R/W 00h 04h F0h R/W 00h IT8661F and IT8661RF Access Mode Configuration Register or Action ISA PnP/MB PnP Parallel Port Activate ISA PnP Parallel Port I/O Range Check ISA PnP/MB PnP Parallel Port Base Address 1 MSB Register ISA PnP/MB PnP Parallel Port Base Address 1 LSB Register ...
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... When the ECP mode is not enabled, this register is READ-only as “04h”, and cannot be written. *4: When the bit 2 of the base address of Parallel Port is set to 1, the EPP mode cannot be enabled. Bit 0 of this register is always 0. IT8661F and IT8661RF Access Mode Configuration Register or Action ...
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... LDN=1 SERIAL PORT 1 LDN=2 SERIAL PORT 2 LDN=3 PARALLEL PORT LDN=4 IR IT8661F and IT8661RF base I/O address range of each logical device. If there are any I/O port conflicts, PnP OS will automatically re-allocate one of the conflicting ports within the base I/O range. Base I/O Range [0X0100:0X0FF8] ON 8-BYTE BOUNDARIES ...
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... This register is the Chip ID byte 2 and for READ-only. Bits[7:0]=61h when read. 6.6.11 Chip Version & Multi-Chips Clarification (Index=22h, Default=00h, MB PnP) This register is the Chip Version. Bits 7,6,3,2,1 are reserved and READ-only. Bits 5 and 4 are writeable and used to clarify different systems that use the same IT8661F or IT8661RF 18 I/O ...
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... If only one IT8661F or IT8661RF chip is implemented, the configuring sequence is not affected by these two (2) bits. Bit 0 is READ only and represents the chip version, as IT8661F if set to “0” and as IT8661RF if set to “1”. 6.6.12 PnP Logical Device Enable Register (Index=23h, Default=00h, MB PnP) The logical devices will not be involved in the ISA PnP protocol sequence except when the enable bits of the PnP logical devices are set ...
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... Enable I/O Range Check. If set, then I/O Range Check is enabled. Before set, FDC should be inactive set, the IT8661F and IT8661RF are forced to respond with a “55h” to I/O READ of the assigned I/O range of FDC when I/O Range Check is in operation. If cleared, it then sends an “AAh” in response. ...
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... I/O Range Check 1 : enable 0 : disable Serial Port 1 must be inactive before set set, the IT8661F and IT8661RF are forced to respond a “55h” to I/O READ of the assigned I/O range of Serial Port 1 when I/O Range Check is in operation. If cleared, it then sends an “AAh” in response. IT8661F and IT8661RF 6 ...
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... I/O Range Check 1 : enable 0 : disable Before set, Serial Port 2 should be inactive set, the IT8661F and IT8661RF are forced to respond a “55h” to I/O READ of the assigned I/O range of Serial Port 2 when I/O Range Check is in operation. If cleared, it then sends an “AAh” in response. 6.9.3 Serial Port 2 Base Address MSB ...
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... I/O Range Check 1 : enable 0 : disable Parallel Port must be inactive before set set, the IT8661F and IT8661RF are forced to respond with a “55h” to I/O READ of the assigned I/O range of Parallel Port when I/O Range Check is in operation. If cleared, it then sends an “AAh” in response. ...
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... Reserved 1 Enable I/O Range Check. If set, then I/O Range Check is enabled. Before set, IR should be inactive set, the IT8661F and IT8661RF are forced to respond with a “55h” to I/O READ of the assigned I/O range of IR when I/O Range Check is in operation. If cleared, it then sends an “AAh” in response. ...
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... Fh-Ch : not valid Bh : IRQ11 . . 3h : IRQ3 2h : not valid 1h : not valid interrupt selected IT8661F and IT8661RF 6.11.10 IR Interrupt Type 2 (Index=73h, Default=02h, ISA PnP) (IT8661RF only) This register indicates the type of interrupt used for IR, and is READ-only as “02h” (to indicate the traditional interrupt type, edge trigger). ...
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... IRQ sharing enabled 0 : Normal IRQ output 4 SIR Mode Select 1 : ASKIR 0 : HPSIR (This bit is available for IT8661F only Half Duplex for SIR or ASKIR 0 : Full Duplex for SIR or ASKIR Dual DMA Channel One DMA channel is for transmitting and the other one is for receiving. ...
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... GPIO[7:0] Pin Polarity Register (Index=F0h, Default=00h, MB PnP) Bit Description 7-0 For each bit 1 : inverting 0 : non-inverting IT8661F and IT8661RF 6.12.11 CS0/CS1/CS2 Control Register (Index=F1h/F2h/F3h, Default=00h, MB PnP) Bit Description 7-6 Base Address Alignment 00 : single port ports ports ...
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... Reserved 4 EPP Port (Parallel Port Base Address + 3h~7h) 3 SPP & ECP Port 2 Serial Port 2 1 Serial Port 1 0 FDC IT8661F and IT8661RF 6.12.16 GPIO[12:8] Pin Polarity Register (Index=F8h, Default=00h, MB PnP) This register is used GPIO[12:8] pin type as polarity inverting or non-inverting for GPIO[12:8]. Bit Description 7-5 ...
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... GPIO 9 (pin 98) 0110 GPIO 10 (pin 19) 1000 GPIO 11 (pin 25) 1010 GPIO 12 (pin 26) 0001 GPIO 0 (pin 86) 0011 GPIO 1 (pin 87) 0101 GPIO 2 (pin 88) 0111 GPIO 3 (pin 89) 1001 GPIO 4 (pin 90) 1011 GPIO 5 (pin 91) 1101 GPIO 6 (pin 92) 1111 GPIO 7 (pin 93) else Reserved IT8661F and IT8661RF 29 ...
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... Functional Description 7.1 General Purpose I/O The IT8661F and IT8661RF provide a set of flexible I/O control and special functions for system designers through a set of General Purpose I/O pins (GPIO). All thirteen (13) GPIO pins are multi-function pins. They will not perform GPIO functions unless the bits of the GPIO function pin enable registers (Index 25h & ...
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... D-FF WR_ IDX F5h (or FAh) RD_ Simple I/O Register GP Interrupt Bit-n Note: All GPIO pins are internally pulled Figure 7-1. General Logic of GPIO Function IT8661F and IT8661RF 1 IDX F6h 1 2 IDX F1h 3 IDX F2h 2 4 IDX F3h 3 IDX F4h IDX F0h 4 (or F9h) ...
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... Reserved 2 - Reserved 1 DBB Drive B Busy Is set high when drive the SEEK portion of a command. 0 DAB Drive A Busy It is set high when drive the SEEK portion of a command. IT8661F and IT8661RF Description Description 32 ...
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... MHz clocks for four (4) different data transfer rates. The bits are defined below: Table 7-4. Diskette Control Register (DCR) Bit 0 Bit 1 Transfer Rates 0 0 500K bps 1 0 300K bps 0 1 250K bps bps IT8661F and IT8661RF Description Clock Rates Reduce Write 8 MHz 0 4.8 MHz 1 4 MHz 1 16 MHz 1 33 ...
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... WRITE-protected diskette. 1. The FDC cannot find a data address mark on the specified track or Deleted Data Address mark. 2. The FDC cannot find any ID address on the specified track after two (2) index pulses are detected from the INDEX # pin. 34 IT8661F and IT8661RF Description Description ...
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... US1 Unit Select. Indicates the current status of the Unit Select signals to FDD. 0 US0 IT8661F and IT8661RF Table 7-7. Status Register 2 Description Unused, this bit is always "0." When the FDC finds a Delete Data Address mark with a READ DATA or SCAN command, this flag bit is set. ...
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... Reset The IT8661F and IT8661RF implement two (2) types of reset on FDC: software and hardware. Either will perform FDC RESET, releasing the FDC to idle state. Attempting a RESET while writing to the disk will cause corruption of data and CRC. (1) Hardware Reset (Reset Pin) With this RESET, all registers of the FDC CORE are cleared (except those programmed by the SPECIFY Command) ...
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... SK stands for Skip Deleted Data Address Mark. SRT Step Rate Time SRT stands for the Stepping Rate for the FDD increments.) Stepping Rate applies to all drives. (F=1 ms, E=2 ms, etc.) IT8661F and IT8661RF Description controls selection of Main Status Register (A stands for the most significant bit, and D 7 ...
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... During a SCAN operation, if STP = 1, the data in contiguous sectors is STP compared byte by byte with data sent from the processor (or DMA); and if STP = 2, then alternate sectors are read and compared. US0, US1 Unit Select US stands for a selected drive number IT8661F and IT8661RF Description ...
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... HDS DS1 39 IT8661F and IT8661RF Final Sector Read from Disk 8 at side Remarks D0 0 Command Codes DS0 Sector ID information before the command execution Data transfer between the FDD and the main system. Status information after ...
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... W ___________________________ GPL_____________________________ W ___________________________ DTL_____________________________ Execution Result R ___________________________ ST0_____________________________ R ___________________________ ST1_____________________________ R ___________________________ ST2_____________________________ R ____________________________ C ______________________________ R ____________________________ H ______________________________ R ____________________________ R ______________________________ R ____________________________ N ______________________________ IT8661F and IT8661RF Data Bus HDS DS1 DS0 40 Remarks Command Codes Sector ID information before the ...
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... W ___________________________ GPL_____________________________ W ___________________________ DTL_____________________________ Execution Result R ___________________________ ST0_____________________________ R ___________________________ ST1_____________________________ R ___________________________ ST2_____________________________ R ____________________________ C ______________________________ R ____________________________ H ______________________________ R ____________________________ R ______________________________ R ____________________________ N ______________________________ IT8661F and IT8661RF Data Bus HDS DS1 DS0 41 Remarks Command Codes Sector ID information before the ...
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... W ___________________________ GPL_____________________________ W ___________________________ DTL_____________________________ Execution Result R ___________________________ ST0_____________________________ R ___________________________ ST1_____________________________ R ___________________________ ST2_____________________________ R ____________________________ C ______________________________ R ____________________________ H ______________________________ R ____________________________ R ______________________________ R ____________________________ N ______________________________ IT8661F and IT8661RF Data Bus HDS DS1 DS0 42 Remarks Command Codes Sector ID information before the ...
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... W ___________________________ GPL_____________________________ W ___________________________ DTL_____________________________ Execution Result R ___________________________ ST0_____________________________ R ___________________________ ST1_____________________________ R ___________________________ ST2_____________________________ R ____________________________ C ______________________________ R ____________________________ H ______________________________ R ____________________________ R ______________________________ R ____________________________ N ______________________________ IT8661F and IT8661RF Data Bus HDS DS1 DS0 43 Remarks Command Codes Sector ID information before the ...
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... R ____________________________ C ______________________________ R ____________________________ H ______________________________ R ____________________________ R ______________________________ R ____________________________ N ______________________________ R Control Commands A special feature of these commands is that they don’t transfer any data. Only three (3) generate interrupts when finished (READ ID, RE-CALIBRATE, and SEEK). IT8661F and IT8661RF Data Bus ...
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... RE-CALIBRATE command will be needed to retract the head to the physical track 0. Table 7-18. Description of the RE-CALIBRATE Command Phase R Command Execution IT8661F and IT8661RF Data Bus HDS DS1 DS0 Data Bus ...
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... SENSE INTERRUPT command be issued after each SEEK command, providing verification of the head position. Table 7-19. Description of the SEEK Command PHASE R Command ___________________________ NCN_____________________________ Execution IT8661F and IT8661RF Data Bus HDS DS1 DS0 46 Remarks ...
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... ST3_____________________________ Interrupt Identification Data Bus Data Bus HDS DS1 47 IT8661F and IT8661RF Remarks D0 0 Command Codes Status information at the end of each seek operation Remarks D0 0 Command Codes DS0 Status information about FDD ...
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... Bit 6 and bit 7 in the Main Status Register are both high. When the CPU reads Status Register 0 it will find an 80H. Table 7-24. Description of the INVALID Command Phase R Command W ________________________invalid codes__________________________ Result R ___________________________ ST0_____________________________ IT8661F and IT8661RF Data Bus ____________HUT_____________ ND ...
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... Serial Channel Register Description The IT8661F and IT8661RF incorporate two (2) enhanced serial channels which perform serial to parallel conversion on received data, and parallel to serial conversion on transmitted data. Individually, they contain a programmable baud rate generator which is capable of dividing the input clock by a number from 1 to 65535 ...
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... Available Character Time-out Indication Transmitter Holding Transmitter Holding Register Empty Register Empty Modem Status CTS#, DSR#, RI#, RSLD# 50 IT8661F and IT8661RF Interrupt Reset Control - LSR READ RBR READ or FIFO drops below the trigger level RBR READ IIR READ if THRE is the Interrupt Source or ...
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... The output frequency is 16X data rate. IT8661F and IT8661RF (5) Scratch Pad Register (READ/WRITE) This 8-bit register does not control the operation of UART in any way intended as a scratch pad register to be used by programmer to temporarily hold general purpose data ...
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... LCR(3): A parity bit, between the last data word bit and stop bit, will be generated or checked (transmit or receive data) when LCR(3) is high. LCR(2) specifies the number of stop bits in each serial character, summarized as follows: IT8661F and IT8661RF LCR (2) Word Length No. of Stop Bits bits ...
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... MCR(1): Controls the Request to Send (RTS#) which inverse logic state with that of MCR(1). MCR(0): Controls the Data Terminal Ready (DTR#) which inverse logic state with that of the MCR(0). IT8661F and IT8661RF Logic 1 Logic 0 Loop Enabled Loop Disabled INT Enabled ...
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... MSR(6): Ring Indicator (RI#) - Indicates the complement to the RI# input. If MCR(4)=1, MSR(6) is equivalent to OUT1 in the MCR. MSR(5): Data Set Ready (DSR#) - Indicates that the modem is ready to provide received IT8661F and IT8661RF LSR(1): Overrun indicates by a logic 1 that the RBR has been overwritten by the next character before it had been read by the CPU ...
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... MSR(3) DRLSD MSR(2) TERI MSR(1) DDSR MSR(0) DCTS 7.3.4 Reset Reset of IT8661F and IT8661RF should be held to an idle mode reset high for 500ns until initialization causes the following: 1. Initialization of the transmitter receiver internal clock counters. Table 7-31. Reset Control of Registers and Pinout Signals ...
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... Programming Each serial channel of IT8661F and IT8661RF is programmed by control registers, whose contents define the character length, number of stop bits, parity, baud rate and modem interface. Even though the control register can be written in any order, the IER should be last because it controls the interrupt enables. After ...
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... Character error status is handled the same way as in the interrupt mode. The IIR is not affected since IER(2)=0. LSR(0): Will be high whenever the RCVR FIFO contains at least one byte There is no trigger level reached or time-out condition indicated in the FIFO Polled Mode. IT8661F and IT8661RF 57 ...
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... Parallel Port The IT8661F and IT8661RF incorporate one multi-mode high performance parallel port. The IT8661F and IT8661RF support the IBM AT, PS/2 compatible bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP). Refer to Table 7-32. Parallel Port Connector in Different Modes Host Connector Pin No ...
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... This bit is cleared by a RESET or writing a logic “1” to it. When IT8661F and IT8661RF are selected to non-EPP mode(SPP or ECP), this bit is always logic "one" (1) when read. (3) Control Port (Base Address 1 + 02h) This port provides all output signals to control the printer ...
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... EPP DATA WRITE 1. The host writes a byte to the EPP Data Port (Base address +04H - 07H). The chip drives D0- D7 onto PD0 -PD7. IT8661F and IT8661RF 2. The chip drives IOCHRDY low and asserts WRITE# (STB#) and DSTB(AFD#) after IOW becomes active. 3. Peripheral de-asserts WAIT#, indicating that the chip may begin the termination of this cycle ...
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... The IT8661F and IT8661RF do not support hardware compression. For a detailed description, Table 7-34. Bit Map of the ECP Registers Register D7 D6 data PD7 PD6 ecpAFifo Addr/RLE dsr nBusy nAck dcr 1 1 cFifo ecpDFifo tFifo cnfgA 0 0 cnfgB 0 intrValue ecr ...
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... The host may drive this signal low to place PD bus in the reverse direction. In ECP mode, the peripheral is permitted to drive the PD bus when nInit is low and nSelect is high Always inactive (high) in ECP mode 62 IT8661F and IT8661RF ...
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... PD bus is in output operation; setting it high, in input operation. This bit will be forced to low in mode 000. IT8661F and IT8661RF dcr(4): Setting this bit high enables interrupt request from peripheral to host due to a rising edge of the nAck input. ...
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... READ/WRITE 1: Disables DMA and all service interrupts 0: Enables the service interrupts. This bit will be set to one (1) by hardware when IT8661F and IT8661RF (13) Extended Control Register (ecr) (Base 2+02h, Mode All) ECP function control register. ecr(7)~ecr(5): These bits are used for READ/WRITE and Mode selection ...
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... ECP address/RLE bytes may be automatically sent by writing the ecpAFifo. Similarly, data PWords may be automatically sent via ecpDFifo. IT8661F and IT8661RF To change directions, the Host switches mode to 001. It then negotiates either the forward or reverse channel, sets direction and finally switches mode to 001. If the direction is ...
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... Although the ISA bus of PC cannot be directly controlled, the interface bandwidth of ECP port can be constrained to perform at optimum speed. IT8661F and IT8661RF (19) Standard Parallel Port In the forward direction with DMA, the standard parallel port is run at or near the permitted peak bandwidth of 500KB/sec. The ...
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... FIR Receive Operation Receiving logic facilities: (1) Receive control circuitry. (2) Receive Byte Count Register to keep track of received bytes. IT8661F and IT8661RF (3) Receive FIFO bits 8-bit data 3-bit status: Frame Error, Abort and End Of Frame. (4) Receive Ring Frame Counter to keep track of the Rx byte number in the host Rx buffer. ...
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... End of Frame bit will be set, when the closing flag is detected. (2) CRC pattern is checked. Frame error is set if CRC is wrong. IT8661F and IT8661RF T6: Post Frame phase: (1) DAM request continues until all the received data in the FIFO has been transferred. Two (2) more bytes in the following format will be ...
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... Base + 4h Timer Register 2 Base + 5h Infrared Configuration 3 Register 2 Base + 6h Reserved 2 Base + 7h Reserved IT8661F and IT8661RF READ Master Control Register Miscellaneous Control Register Tx FIFO Register Tx Control 1 Register Tx Control 2 Register Rx Control Register Reset Command Register Master Control Register Address Register Tx Byte Count Low Register ...
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... FIR controller transmit and receive data paths. Bit 4 4Mbit Loopback When set to ‘1’, the 4Mbit modem transmits data output signal is internally looped back to its receive data input. This allows for 70 IT8661F and IT8661RF ID2-ID0 which provide Priority ...
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... Auto Reset RTS Setting this bit to ‘1’ enables automatic deactivation of the modem Request To Send line at the end of transmission. IT8661F and IT8661RF For back-to-back transmission desirable that the Request To Send signal remains active for the entire duration in which packets are transmitted ...
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... Tx Byte Count value is greater than zero). This bit must be reset by an explicit FIFO UNDERRUN/EOM command. IT8661F and IT8661RF Bit 2 End of Message (EOM) When set to ‘1’, indicates transmission completed successfully. The EOM interrupt occurs immediately after the CRC and ending flag have been transmitted ...
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... Sync/Hunt Change bit. If bit Control Register is disabled, reading Rx Status register will directly provide the status of the Sync/Hunt signal and will not clear the Sync/Hunt Change bit. Bits 1-0 Reserved 73 IT8661F and IT8661RF bit is automatically cleared Register after the ...
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... IT8661F and IT8661RF (14) Rx Byte Count High Register (Bank=1h, Base Address+3h, READ-only) Bits 7-5 Reserved Bits 4-0 Rx Byte Count, D12-D8 Provides a running count (high-order value) of the number of bytes of data being received useful packets D12 ...
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... Mbps IrDA Reserved Mbps IrDA IT8661F and IT8661RF (20) Infrared Transceiver Control Register (Bank=2h, Base Address+2h, READ/WRITE) Bits 7-6 Reserved Bit 5 High/Low Data Frequency When an HP-like transceiver is selected in the configuration register, high or low infrared data frequency is determined by this bit. ...
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... Setting this bit to ‘1’ causes SIR interrupt request to be masked. Bit 0 Disables FIR Interrupt Setting this bit to ‘1’ causes FIR interrupt request to be masked. IT8661F and IT8661RF Effect Chopping circuit is disabled. Extend the single pulse width tolerance to 187ns. Back-to-back pulses must be greater than 209ns ...
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... Bit 1 Enable Timer Interrupt Setting this bit to ‘1’ enables Timer Interrupt. Bit 0 Timer Interrupt When set to ‘1’, indicates a timer interrupt is pending. To clear the interrupt, software must WRITE a ‘1’ to this bit. This bit is self-clearing. IT8661F and IT8661RF ...
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... Output High Voltage OH O24 Type Buffer V Output Low Voltage OL V Output High Voltage OH IT8661F and IT8661RF *Comments Stresses above those listed under “Absolute +0.3V CC Maximum damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in +0 ...
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... High Input Leakage IH OCLK Type Buffer V Low Output Voltage OL V High Output Voltage OH ICLK Type Buffer V Low Input Voltage IL V High Input Voltage IH I Low Input Leakage IL I High Input Leakage IH IT8661F and IT8661RF Min. Typ. Max. 0.4 2.4 0.4 2.4 0.8 2.0 10 -10 0.4 2.4 0.8 2.0 10 -10 79 Unit Conditions V ...
Page 89
... IOW # Table 9-2. WRITE Cycle Timing Symbol Parameter t1 Address setup to IOW# t2 Address hold from IOW# t3 IOW# pulse width t4 Data setup to IOW# t5 Data hold from IOW# IT8661F and IT8661RF 5 Valid Data Min. Typ. Max 100 25 65 ...
Page 90
... The DMA Channel is selected by the configuration register (0X74). 9.3.2 Terminal Count, Index TC INDEX# Table 9-4. Terminal Count, Index of FDC Timing Symbol Parameter t1 Terminal count width t2 INDEX# pulse width t1 Min. Typ Min. Typ. 80 100 81 IT8661F and IT8661RF Max. Unit 100 Max. Unit ns ns ...
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... SEEK Operation Timing DIR # t3 STEP Table 9-6. SEEK Operation Timing of FDC Timing Symbol Parameter t1 STEP# active time t2 STEP# cycle time t3 DIR# setup to STEP# Min. Typ. 396/248/ 252 248/396/ 748 t2 t1 Min. Typ. 6 6.104 1 82 IT8661F and IT8661RF Max. Unit ns ns Max. Unit ...
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... Delay from initial write to IRQx active t4 Delay from stop (SOUT) to IRQx (THRE) t5 Delay from IOR# (RD IIR) to reset IRQx (THRE) START STOP DATA(5-8) PARITY ( 1-2 ) Min. Typ. Max IT8661F and IT8661RF START DATA( 5- Unit Baud cycle 24 baud cycle 24 baud cycle 100 ns ...
Page 93
... Delay from IOW# (WR MCR) to output (RTS# or DTR#) low t3 Delay to set interrupt IRQx from MODEM input (CTS#, RLSD#, DSR#) t4 Delay to reset interrupt IRQx from IOR# (RD MSR) t5 Delay to set interrupt IRQx from MODEM input (RI#) IT8661F and IT8661RF Min. Typ. Max ...
Page 94
... Bit Time at 57.6 kbaud t2 Bit Time at 38.4 kbaud t2 Bit Time at 19.2 kbaud t2 Bit Time at 9.6 kbaud t2 Bit Time at 4.8 kbaud t2 Bit Time at 2.4 kbaud Note: IrDA @ 115k is HPSIR compatible. IrDA @ 2400 will allow compatibility with HP95LX and 48SX. IT8661F and IT8661RF PARITY STOP t1 ACTIVE Min. Typ. Max ...
Page 95
... Bit Time at 4.8 kbaud t2 Bit Time at 2.4 kbaud Note: Criteria for Receive Pulse Detection - A received pulse is considered detected if the pulse width is 1.4 ms minimum. 9.4.6 ASKIR Receive Timing 1 DATA IRRXL t3 t4 MIRSIN IT8661F and IT8661RF BIT TIME t2 Min. Typ. Max. 1.41 1.6 2.71 2.82 3 ...
Page 96
... Modulated Output Bit Time t2 Off Bit Time t3 Modulated Output "high" t4 Modulated Output "low" Note: MIRSOUT is the modulated output. 9.5 Parallel Port Timing 9.5.1 Control Signal Delay Time IOW CTRL ) STB#,AFD# INIT#,SLIN# IT8661F and IT8661RF Min. Typ. Max. 0.8 1 1.2 0 Min. ...
Page 97
... Delay from IOW# (WR CTRL PORT) to SLIN# valid 9.5.2 Interrupt Request Timing ACK# t1 IRQx Table 9-15. Interrupt Request Timing of Parallel Port Timing Symbol Parameter t1 Delay from ACK# to IRQx t2 Delay from ACK# to IRQx IT8661F and IT8661RF Min. Typ. Max Min. Typ. Max Unit ...
Page 98
... WAIT# deasserted to IOCHRDY asserted t8 ASTB# or DSTB# deasserted to WAIT# asserted t9 WAIT# asserted to WRITE# deasserted t10 PD[7:0] invalid after WRITE# deasserted Min. Typ IT8661F and IT8661RF t10 t9 Max. Unit 135 ns 135 ...
Page 99
... EPP Address or DATA READ Cycle AEN A[ 15 7:0 ] IOR# t1 IOCHRDY WRITE# t2 ASTB# DSTB# WAIT# PD[ 7 IT8661F and IT8661RF t10 ...
Page 100
... WAIT# deasserted to IOCHRDY deasserted t8 ASTB# or DSTB# deasserted to WAIT# deasserted t9 PD[7:0] invalid after ASTB# or DSTB# deasserted t10 D[7:0] invalid after IOR# deasserted 9.8 ECP Parallel Port Forward Timing Diagram PD[7:0] nAutoFd t1 nStrobe Busy IT8661F and IT8661RF Min. Typ. Max 135 65 135 0 20 ...
Page 101
... PD[7:0] & busy changed t6 nAutoFd deasserted to nAck asserted Note: Maximum value only applies if there is room in the FIFO and terminal count has not been received. ECP can stall by keeping nAUTOFD low. IT8661F and IT8661RF Min. Typ. Max 180 ...
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... NOM. 18.85 NOM. 0.693 NOM. 17.60 NOM. 0.929 NOM. 23.60 NOM. 0.740 0.012 18.80 0.976 0.012 24.79 0.047 0.008 1.19 0.095 0.008 2.41 0.006 Max. 0.15 Max & G are for PC Board surface mount pad pitch design IT8661F and IT8661RF Detail F 1 0.13 0.05 0.05 0.13 0.13 0.15 0.31 0.31 0.20 0.20 ...
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... Ordering Information Part No. Supports IT8661F IT8661RF MIR or FIR Package MIR 100L QFP 100L QFP 94 IT8661F and IT8661RF ...