CA91L8260B-100CL Tundra Semiconductor, CA91L8260B-100CL Datasheet
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... Document Number: 80A1010_MA001_06 Document Status: Final Release Date: December 2002 This document discusses the features, capabilities, and configuration requirements of the PowerSpan II intended for hardware and software engineers who are designing system interconnect applications with the PowerSpan II. Tundra Semiconductor Corporation ™ ...
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... Trademarks TUNDRA is a registered trademark of Tundra Semiconductor Corporation (Canada, U.S., and U.K.). TUNDRA, the Tundra logo, PowerSpan II, and Silicon Behind the Network, are trademarks of Tundra Semiconductor Corporation. All other registered and unregistered marks (including trademarks, service marks and logos) are the property of their respective owners. The absence of a mark identifier is not a representation that a particular product name is not a mark ...
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... Corporate Profile Tundra Semiconductor Corporation Tundra Semiconductor Corporation (TSE:TUN) designs, develops, and markets advanced System Interconnect for use by the world’s leading Internet and communications infrastructure vendors. Tundra chips provide the latest interface and throughput features to help these vendors design and deliver more powerful equipment in shorter timeframes ...
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... Tundra can anticipate and meet the future directions and needs of communications systems designers and manufacturers. Tundra Customers Tundra semiconductor products are used by the world's leading communications infrastructure vendors, including Cisco, Motorola, Ericsson, Nortel, Lucent, IBM, Xerox, Hewlett-Packard, 3Com, Nokia, Siemens, Alcatel, Matsushita, OKI, Fujitsu, Samsung, and LGS ...
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Contact Information Tundra is dedicated to providing its customers with superior technical documentation and support. The following types of support are available: Webpages Product information Design Support Tools (DST) FAQ database Sales support PowerSpan II Bus Switch User Manual 80A1010_MA001_06 ...
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... PowerSpan II Bus Switch User Manual. Use docs@tundra.com to order printed copies of Tundra product manuals (Final status only). Please include PowerSpan II in the subject header of your message. 613-592-0714 or 1-800-267-7231 613-592-1320 Tundra Semiconductor Corporation 603 March Road Kanata, ON K2K 2M5 PowerSpan II Bus Switch User Manual 80A1010_MA001_06 ...
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Contents Corporate Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 2. PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Processor Bus Interface 101 3.2 Interface Support . . . . . ...
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Contents 5.4 PCI Vital Product Data (VPD ...
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Endian Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 10.2 ...
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Contents 12.3.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . 280 12.3.2 Handling and Storage Specifications . . . . . . . . ...
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C.4 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 14 PowerSpan II Bus Switch User Manual 80A1010_MA001_06 ...
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List of Figures Figure 1: PowerSpan II Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 27: 484 PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: PowerSpan II Applications ...
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List of Tables Table 27: PowerSpan II PB Transfer Sizes ...
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Table 62: PCI-2 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 97: PCI-2 AD[31:11] lines asserted during Configuration Type 0 cycles . . . 331 Table 98: PCI 1 to PCI-2 Configuration Cycle Data Register . . . . . . . . . . . . ...
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Table 130: Miscellaneous Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . 378 Table 131: Arbitration Pin Mappings ...
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List of Tables Table 165: I2O Inbound Post List Bottom Pointer Increment Register . . . . . . . . . . . 429 Table 166: I2O Inbound Post List Top Pointer Register . . . . . . ...
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Table 200: PB Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables 24 PowerSpan II Bus Switch User Manual 80A1010_MA001_06 ...
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About this Document This chapter discusses general document information about the PowerSpan II User Manual. The following topics are described: • “Revision History” on page 25 • “Document Conventions” on page 26 • “Related Documents” on page 28 Revision History ...
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About this Document Document Conventions This section explains the document conventions used in this manual. Signal Notation Signals are either active high or active low. Active low signals are defined as true (asserted) when they are at a logic low. ...
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Typographic Notation The following typographic conventions are used in this manual: • Italic type is used for the following purposes: — Book titles: For example, PCI Local Bus Specification. — Important terms: For example, when a device is granted access ...
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About this Document Related Documents The following documents are useful for reference purposes when using this manual. PCI Local Bus Specification (Revision 2.2) PCI-to-PCI Bridge Architecture Specification (Revision 1.1) PCI Bus Power Management Interface Specification (Revision 1.1) CompactPCI Hot Swap ...
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Functional Overview This chapter describes the PowerSpan II’s architecture. The following topics are discussed: • “PCI Interface” on page 35 • “Processor Bus Interface” on page 37 • “DMA Controller” on page 38 • “I2C / EEPROM” on page ...
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Functional Overview The high level of performance and flexibility of PowerSpan II is made possible through Switched PCI - unique to PowerSpan II. Switched PCI uses a switching fabric to enable data streams to pass from port-to-port across the ...
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... CompactPCI Hot Swap Friendly • PCI 2.2 Specification compliant 1.1.1.3 Packaging options • Single PCI PowerSpan II (CA91L8260B) — 64-bit/66MHz — 420 HSBGA: 1.27mm ball pitch, 35mm body size — 484 PBGA: 1.0mm ball pitch, 23mm body size • Dual PCI PowerSpan II (CA91L8200B) — 32-bit/66MHz and 64-bit/66MHz ...
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Functional Overview — 480 HSBGA: 1.27mm ball pitch, 37.5mm body size — 504 HSBGA: 1.0mm ball pitch, 27mm body size 1.1.2 PowerSpan II Benefits PowerSpan II offers the following benefits to designers: • Smaller packages reduce board area required ...
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PowerSpan very flexible device. The following diagram shows a typical PowerPC system architecture using PowerQUICC II and the Dual PCI PowerSpan II. Figure 2: Typical PowerSpan II Application MPC8260 Memory Controller Processor Bus 32-bit Address / 64-bit ...
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Functional Overview 1.1.4 PowerSpan II and PowerSpan Differences Summary The following table summarizes the main PowerSpan II programmable features that were unavailable in the PowerSpan device. All functional enhancements are programmable in order to make sure that all original ...
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Table 2: PowerSpan II Functional Enhancements Functional Enhancement Descriptions Arbitration Timing for Masters PowerSpan II measures the length of time it takes a master to respond to the GNT# signal. PowerPC 7400 Transaction Support PowerSpan II has been designed to ...
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Functional Overview 1.2.1 PCI-to-PCI Bridge The Dual PCI PowerSpan PCI-to-PCI bridge. It connects traffic between the two PCI interfaces. This PCI-to-PCI bridging function is “non-transparent” non-transparent bridge one PCI bus is hidden from system ...
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... This verification ensures any potential interface issues are identified and resolved by Tundra Semiconductor before PowerSpan II customers begin to design their own systems. PowerSpan II supports MPC8260 extended cycles on the Processor Bus Interface. ...
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Functional Overview 1.3.2 Processor Bus Arbitration The Processor Bus Interface has an integrated bus arbiter. The Processor Bus Interface supports three external bus masters for applications involving multiple processors. The processor bus arbiter implements two levels of priority, where ...
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PowerSpan II’s Concurrent Read Solution With PowerSpan II’s concurrent reads, read requests are accepted even while the current read is in progress. PowerSpan II. Figure 4: Concurrent Read Process with PowerSpan II READ 1 Request 1. Master 1: Makes ...
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Functional Overview 1.6.1.1 Conventional Reads and Retries In conventional FIFO-based bridge architectures, bus masters must take turns for read opportunities and incur multiple retries while waiting. read process for subsequent reads where retries are incurred while a pending read ...
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PowerSpan II’s Concurrent Read Applications 1.6.2.1 PCI Host Bridge In a PCI host bridge application, all of the PCI masters controllers potentially receive only one retry before receiving read data. Even — with another read pending, when the PCI ...
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Functional Overview 42 PowerSpan II Bus Switch User Manual 80A1010_MA001_06 ...
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PCI Interface Peripheral Component Interconnect (PCI bus protocol that defines how devices communicate on a peripheral bus and with a host processor device is referred to as PCI compliant it must be compliant with the ...
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PCI Interface — One 32-bit interface — 66 MHz operation • Single PCI PowerSpan II: — One 32-bit or 64-bit PCI interface — 66 MHz operation 2.1.1 Primary PCI The Dual PCI PowerSpan II has two PCI interfaces: the ...
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The speed of these buses is determined through a power-up option (see page 205 and “Power-Up Options” on page P1_M66EN pins. Both PCI interfaces run asynchronously to one another, and asynchronously to the Processor Bus Interface. 2.1.2 PCI Data Width ...
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PCI Interface In non-Hot Swap applications, the P1_64EN# signal must be pulled high in order to enable sampling of P1_REQ64# to determine the width of the data path. The result of the sampling of P1_REQ64# is or’d with the ...
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P1_CBE[7:4] — P1_REQ64# — P1_ACK64# — P1_PAR64 — P1_AD[63:32] — P1_CBE[7:4] — P1_PAR64 • Driven High — P1_REQ64# — P1_ACK64# This insures the signals do not oscillate and that there is not a significant power drain through the input ...
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PCI Interface 2.1.4.1 Transactions Between Px and Py PowerSpan II implements the following transaction ordering rules for transactions flowing between PCI Interface Px and PCI Interface Py: • The order in which delayed read requests are latched on the ...
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DMA Transactions DMA transactions and regular write/read transactions arbitrate for the use of a master interface in a round robin scheme. There are no special priorities for DMA transactions and regular write/read transactions. Writes and reads from one source ...
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PCI Interface 2.2 PCI Target Interface 2.2.1 PowerSpan II as PCI Target PowerSpan II participates in a transaction as a PCI target when a PCI master initiates one of the following actions: • attempts to access the alternate PCI ...
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Table 4 illustrates the command encoding for PowerSpan II as PCI target. Table 4: Command Encoding for Transaction Type Target Px_C/BE#[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 The PCI target ...
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PCI Interface Table 5 describes the programming model for a PCI Target Image Control register. Table 5: Programming Model for PCI Target Image Control Register Bits Type IMG_EN R/W Enables the PCI target image to decode in the specified ...
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Table 5: Programming Model for PCI Target Image Control Register Bits Type WTT[4:0] R/W A 5-bit value, defined in the processor bus protocol, is generated on the PB_TT lines during a write on the processor bus. PRKEEP R/W Enables PowerSpan ...
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PCI Interface 2.2.2.2 Address Translation The address generated on the destination port is dependent on the use of address translation in the source target image. For more information, see the Translation Address Enable (TA_EN) bit in the page 322. ...
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Data Phase 2.2.3.1 Writes PowerSpan II accepts single beat or burst transactions in memory space. I/O accesses are not decoded. All writes to the PCI Target are posted writes. Burst writes are linear bursts. A Target-Disconnect is issued if ...
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PCI Interface – The PCI Target latches the transaction parameters and issues a retry. 2. Delayed Read – The PCI Target obtains the requested data. The destination bus master retries requested data. 3. Delayed Read Completion – The master ...
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PowerSpan II prefetch behavior on the destination bus when claiming Memory reads on the originating bus is controlled by the PCI Memory Read Alias (MRA) bit and the Prefetch Size (RD_AMT[2:0]) field in the Register” on page read, PowerSpan II ...
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PCI Interface 2.2.3.3 Data Parity PowerSpan II monitors Px_PAR#/Px_PAR64# when it accepts data as a PCI target during a write. PowerSpan II drives Px_PAR#/Px_PAR64# when it provides data as a PCI target during a read. In both cases, the ...
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Target-Retry: A termination is requested — by asserting Px_STOP# and Px_DEVSEL# while Px_TRDY# is high — by the PCI Target because it cannot currently process the transaction. Retry means the transaction is terminated after the address phase without any ...
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PCI Interface 2.3 PCI Master Interface 2.3.1 PowerSpan II as PCI Master In order for PowerSpan PCI master in a transaction the Bus Master (BM) bit, in the “PCI 1 Control and Status Register” on ...
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Arbitration for PCI Bus PowerSpan II issues a bus request on the PCI bus when it requires access to the PCI bus. When the PowerSpan II PCI arbiter is active, this request is internal. When it is not enabled ...
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PCI Interface 2.3.3 Address Phase 2.3.3.1 Command Encoding The encoding on the Px_C/BE# lines indicate the transaction type on the PCI bus. The PCI command encoding supported by PowerSpan II, and their corresponding transaction types, are shown in Table ...
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A new request for access to the bus is generated by the PowerSpan II PCI Master when it requires access to the PCI bus to service a request from the Processor Bus Interface or the other PCI interface (Py). After ...
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PCI Interface The PB Master can also generate MPC8260 extended cycles. Extended cycles are either 16 byte or 24 byte transactions. These cycles are enabled by setting the Extended Cycle (EXTCYC) bit the Processor Bus Miscellaneous ...
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The read amount presented to the PCI Master determines the command used. A Memory Read Line command uses the burst length programmed into the CLINE[7:0] field in the programmable to 16-, 32-, 64-, or 128 bytes. If the PCI Master ...
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PCI Interface 2.3.5 Termination Phase 2.3.5.1 PCI Master Terminations The PCI Master supports all four types of PCI terminations: 1. Master-Abort: The PCI Master negates Px_FRAME# and then negates Px_IRDY# on the following clock edge when no target responds ...
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CompactPCI Hot Swap Silicon Support CompactPCI’s Hot Swap Specification defines the process for installing and removing adapter boards without adversely affecting a running system. It provides a programmatic access to Hot Swap services. This enables system re-configuration and fault ...
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PCI Interface 2.4.3 HEALTHY# Signal PowerSpan II manages the electrical board level issues involved in the Hot Swap process with the HEALTHY# signal. The negation of HEALTHY# indicates only some of the components on the Hot Swap card are ...
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Figure 7: PowerSpan CompactPCI Adapter Card Ensure that PB_CLK and P2_CLK are within specification before the release of Back End power-up reset. PowerSpan II Bus Switch User Manual 80A1010_MA001_06 Connector PCI-1/J1 PCI Compact 2. PCI Interface 69 ...
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PCI Interface 2.4.5 Hot Swap Insertion Process Use the application illustrated in insertion process outlined below. 1. Long pins contact for Early Power: — HEALTHY# negated – PowerSpan II resources are in reset – LED# pin enabled, status diode ...
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MPC8260 completes its configuration master transactions – PowerSpan II power-up options are loaded — MPC8260 HRESET_ times out — PowerSpan II PLL locking complete – All PowerSpan II resources out of reset, PB_RST_ and P2_RST# negated – PowerSpan II ...
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PCI Interface Figure 8: Hot Swap Insertion Long Engage Short Med Engage Engage Early Power Back End Power BD_SEL# Pulled up HEALTHY# PCI RST# pre-charge (from J1) PCI Clock pre-charge PCI Signals pre-charge Engaged, tracking bus Ejector State pre-charge ...
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Sets the LED On/Off (LOO) bit in the P1_HS_CSR register. This causes the assertion of LED# which turns the light emitting diode to signal the operator At this point the operator can close the ejector switch and reenter the ...
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PCI Interface Figure 9: Hot Swap Extraction Ejector Unlatched Early Power Back End Power BD_SEL# HEALTHY# PCI RST# (from J1) PCI Clock PCI Signals Engaged, tracking bus Ejector State Closed Open ENUM# LED LED off INS bit Cleared/Unarmed EXT ...
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Vital Product Data Vital Product Data (VPD) is information which uniquely defines items of a system. These items include the hardware, software and microcode elements of a system. VPD also provides a mechanism for storing information, such as performance ...
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PCI Interface 2.5.2 Reading VPD Data PowerSpan II implements 8-bits of address for accessing the EEPROM maximum of 256 bytes. The VPD address must be DWORD-aligned. A single read access reads four consecutive bytes starting from ...
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I O Shell Interface 2 PowerSpan II provides portions of the I connecting to the Primary PCI bus. The I Specification is comprised of three main sections: • messaging interface • protocol for exchanging messages • executive class messages ...
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PCI Interface 2.6.2 IOP Functionality A number of configuration steps are required before PowerSpan II and the embedded processor bus are enabled to provide IOP functionality. The following example assumes PCI-1 is the Primary PCI Interface. The steps required ...
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Global Command (GBL) in the PCI_TI2O_CTL register. – Cache Inhibit (CI) in the PCI_TI2O_CTL register. — Select endian conversion mechanism with the Endian Conversion (END) bit in the PCI_TI2O_CTL register — Configure address translation – Translation Address Enable (TA_EN) ...
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PCI Interface The I 0 Inbound Queue Register Interface is located at offset 0x040 of the 2 PowerSpan II PCI I Free List FIFO and a Post List FIFO, both of which reside in the IOP local memory. 2.6.3.2 ...
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Protocol for Exchanging Messages PowerSpan The PowerSpan II PCI I registers: • Outbound Post List Interrupt Status Register 2 • Outbound Post List Interrupt Mask Register 2 • Inbound Queue ...
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PCI Interface • Inbound Free List Bottom/Top/Top Increment Pointer Registers: (IFL_BOT/ IFL_TOP/IFL_TOP_INC) — Manages the Inbound Free List circular FIFO implemented in local memory • Inbound Post List Bottom/Bottom Increment/Top Pointer Registers: (IPL_BOT/IPL_BOT_INC/IPL_TOP) — Used to manage the Inbound ...
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Figure 10: PowerSpan Message Passing 2 Inbound Queue (0x040) Local Processor (IOP) PCI Bus Inbound Queue Outbound Queue Outbound Queue (0x044) Local Processor (IOP) The Top and Bottom pointers manage external FIFOs to determine the full and/or ...
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PCI Interface 2.6.4 Inbound Messages The Inbound Free and Post List FIFOs are implemented as circular queues using Bottom and Top pointers. The PowerSpan II implements the Bottom and Top pointers for the Inbound Free List FIFO and the ...
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MFA back to the Top of the Inbound Free List FIFO • writes to the PowerSpan II’s Inbound Free List Top Pointer Increment Register to increment the address by four • reads the IPL bit, in the ...
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PCI Interface • reads the Outbound Queue Register at offset 0x044 of the PowerSpan II I target image map to obtain the next Outbound Post List MFA. • processes the Message pointed to by the MFA. The Outbound Interrupt ...
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The Pull model requires 16 byte alignment of the message frames, therefore, the least significant four bits of the MFA are always zero. The Pull options use these four bits to create an Extended MFA (XMFA). The Pull model uses ...
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PCI Interface 2.6.6.2 Host Free List Address The address and size of the Host Free List FIFO is provided to the IOP by the I System Host Free List FIFO structure is located at a memory ...
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Figure 11: PowerSpan Pull Capability 2 Inbound Queue Step 3 (0x040) Step 6 XMFA Step 5 Local Processor (IOP) PCI Bus Inbound Queue Host Platform XMFA Host Free Step 6 List Index XMFA Step 3 Host Processor ...
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PCI Interface 4. Local processor reads XMFA from the Inbound Post List FIFO 5. Local processor copies MF from Host memory 6. Local processor writes XMFA to Host Free List Index 2.6.7 Outbound Option The I O 2.0 Specification ...
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PowerSpan II also implements a Host Outbound Index Register where the Host will write its Host Outbound Post List FIFO Index after servicing Outbound reply messages posted using the Outbound Option. The Host Outbound Index Register points to the Bottom ...
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PCI Interface Figure 12: PowerSpan Outbound Capability 2 XMFA Step 3 XMFA XMFA Step 5 Host Processor PCI Bus Host Platform Outbound Queue XMFA Outbound Queue Step 5 (0x044) XMFA Step 3 Local Processor (IOP) Figure ...
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Host processor reads the XMFAs from the Host Outbound Post List 5. Host writes the XMFA to the Outbound Queue (0x044) 2.6 Standard Registers 2 This section defines the standard I registers are accessible within the PowerSpan ...
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PCI Interface Table 11: I2O Outbound Post List Interrupt Status Register Register Name: OPL_IS PCI Bits 31-24 23-16 15-08 07- Reserved 2 OPL_IS Description Reset Name Type OPL_ISR R Px_RST The I 0 2.0 Specification requires the ...
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Table 12: I2O Outbound Post List Interrupt Mask Register Register Name: OPL_IM PCI Bits 31-24 23-16 15-08 07-00 I2O Reserved OPL_IM Description Reset Name Type OP_ISM R/W Px_RST The I 0 2.0 Specification requires the Outbound Post_List Interrupt Mask register ...
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PCI Interface Table 13: I2O Inbound Queue Register Name: IN_Q PCI Bits 31-24 23-16 15-08 07-00 IN_Q Description Reset Name Type MFA[31:0] R/W Px_RST MFA: The Inbound Message Frame Address specifies locations in the IOP memory map where Inbound ...
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Table 14: I2O Outbound Queue Register Name: OUT_Q PCI Bits 31-24 23-16 15-08 07-00 OUT_Q Description Reset Name Type MFA[31:0] R/W Px_RST MFA: The Outbound Message Frame Address specify locations in the Host memory map where Outbound Message Frames reside. ...
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PCI Interface Table 15: I2O Host Outbound Index Register Register Name: HOST_OI PCI Bits 31-24 23-16 15-08 07-00 HOST_OI Description Reset Name Type OI[29:0] R/W Px_RST OI: This register indicates the address in Host memory from which the Host ...
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PowerSpan II Bus Switch User Manual 80A1010_MA001_06 2. PCI Interface 99 ...
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PCI Interface 100 PowerSpan II Bus Switch User Manual 80A1010_MA001_06 ...
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Processor Bus Interface This chapter describes the functionality of the Processor Bus Interface. Both the Single PCI PowerSpan II and Dual PCI PowerSpan II have a Processor Bus Interface. The following topics are discussed: • “Overview” on page 101 ...
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Processor Bus Interface These interfaces are not identical, but for the most part, the processor interface on the PowerSpan II is referred to simply as the Processor Bus (PB). The interface sections in this chapter highlight where the PowerSpan ...
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Terminology The following terms are used in the Processor Bus Interface descriptions: • address retry window: refers to the clock following the assertion of AACK_, which is the latest a snooping master can request for an address tenure re-run. ...
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Processor Bus Interface • Data Transfer: This section describes control of transaction length. • Terminations: This section describes the terminations supported by PowerSpan II, and exception handling. The PowerSpan II PB Slave supports cacheable accesses to PCI, but it ...
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PowerSpan II supports eight general purpose slave images and four specialty slave images. A general purpose slave image generates memory or I/O reads and writes to the PCI bus. For example, the eight general purpose slave images can support the ...
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Processor Bus Interface Table 16 describes the bits and default settings of the PB Slave Image Control register (see page Table 16: Programming Model for PB Slave Image Control Register Bits Type Description IMG_EN R/W Enables the PB slave ...
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Table 17: Recommended Memory/Cache Attribute Settings PowerSpan II Resource Registers PCI I/O space PCI Memory space Register and PCI I/O space accesses require I=1 because PowerSpan II does not accept burst transactions to these resources. Master-based Decode Mode The PB ...
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Processor Bus Interface All reads are treated as delayed reads and can be single cycle, extended or bursts. All writes are treated as posted writes and can be single cycle, extended or bursts. PowerSpan II handles address only cycles ...
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Because PowerSpan II does not have a cache, all read and write transfer types are treated the same. For example, a Read with Intent to Modify command (PB_TT= 01110) is handled the same way as a Read Atomic command (PB_TT= ...
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Processor Bus Interface When ARTRY_EN is enabled, the PB Slave asserts PB_ARTRY_ in the following situations: • a write destined for PCI cannot be internally buffered • when a read request has been latched and read data is being ...
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Table 19: Translation Address Mapping PB_SIx_TADDR Processor Bus Address (PB_A) 31 31:30 31:29 31:28 31:27 31:26 31:25 31:24 31:23 31:22 31:21 31:20 31:19 31:18 31:17 31:16 31:15 31:14 31:13 31:12 PowerSpan II Bus Switch User Manual 80A1010_MA001_06 BS bit (PB_SIx_CTL ...
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Processor Bus Interface 3.3.2.5 Address Parity Address parity checking is provided on each byte of the address bus. Address parity bit assignments are defined in Table 20: PowerSpan II PB Address Parity Assignments Address Bus PB_A[0:7] PB_A[8:15] PB_A[16:23] PB_A[24:31] ...
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Data Phase 3.3.3.1 Transaction Length The PB Slave supports a set of the data transfer sizes supported by the embedded PowerPC family. All data transfer sizes supported by the PowerSpan II PB Slave are illustrated in Table Bus Transfer ...
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Processor Bus Interface Table 21: PowerSpan II PB Transfer Sizes Transfer Size Byte Half-word Tri-byte Word Five bytes Six bytes Seven bytes Double Word (DW) Extended Double (MPC8260 only) Extended Triple (MPC8260 only) Burst (Quad DW) 3.3.3.2 Data Alignment ...
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Table 22: PowerSpan II Processor Bus Single Beat Data Transfers Size TSIZ[0:3] A[29:31] Byte 0001 000 0001 001 0001 010 0001 011 0001 100 0001 101 0001 110 0001 111 Half word 0010 000 0010 001 0010 010 0010 011 ...
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Processor Bus Interface Table 22: PowerSpan II Processor Bus Single Beat Data Transfers Size TSIZ[0:3] A[29:31] Word 0100 000 0100 001 0100 010 0100 011 0100 100 Five bytes 0101 000 0101 001 0101 010 0101 011 Six bytes ...
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PowerSpan II supports a specific types of the PowerPC 7400 misaligned transactions (shown in Table 22) when the MODE_7400 bit is set in the Processor Bus Miscellaneous Control and Status register between PowerSpan II and the MPC7400 that is a ...
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Processor Bus Interface Any attempt by a processor bus master to complete the read transaction is retried by the PowerSpan II PB Slave until the following byte quantities are available in the line buffer: • 32 bytes • 8 ...
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There are instances where a read requires more data than that specified by RD_AMT. Since PB slaves cannot terminate transactions, PowerSpan II compensates for a potential hang situation data by over-riding the programming of RD_AMT. PowerSpan II prefetches the — ...
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Processor Bus Interface Address Retry Disabled The PB Slave supports a single read at a time when ARTRY_EN is disabled. ARTRY_EN is disabled by setting the bit to 0. The PB slave acknowledges the address tenure with the PB_AACK_ ...
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The data parity bits, PB_DP[0:7], are driven to the correct values for even or odd parity by the PB slave during reads and checked during writes. The detection of a data parity error does not affect the transaction and data ...
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Processor Bus Interface • Data Valid (PB_DVAL_): This signal is asserted by the PB slave to indicate the successful transfer of an 8-byte quantity within an extended transfer bytes. PB_TA_ is asserted together with PB_DVAL_ ...
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PB Master Interface 3.4.1 PowerSpan Master The PowerSpan II becomes active as PB Master when: • PowerSpan II is accessed as a PCI target • one of the PowerSpan II DMA engines is processing a transfer ...
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Processor Bus Interface The PB Master operates in a multi-processor, cache-coherent PowerPC environment that requires correct implementation of the window of opportunity. The following PB Master behavior supports the window of opportunity: • respond to PB_ARTRY_ in the address ...
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Address Pipelining The PB Master can operate in a system that implements up to one level of address pipelining. The PB Master does not prohibit other bus agents from pipelining transactions. When mastering the bus, the PB Master can begin ...
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Processor Bus Interface The default transfer type generated by the PowerSpan II PB Interface master is shown in Table 25. Table 25: Default PowerSpan II PB Master Transfer Type PB Master Transaction Writes Reads 3.4.2.4 Address Parity Address parity ...
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PB_ARTRY_ negated • Data bus not busy External slaves must not indicate a successful data transfer with the assertion of PB_TA_ and/or PB_DVAL_ earlier than two clocks after the assertion of PB_TS_. To ensure MPC8260 compliance with this rule, ...
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Processor Bus Interface Table 27: PowerSpan II PB Transfer Sizes Transfer Size Byte Half-word Tri-byte Word Five bytes Six bytes Seven bytes Double Word (DW) Extended Double (MPC8260 only) Extended Triple (MPC8260 only) Burst (Quad DW) The following figures, ...
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Figure 14: PB Master Interface Burst Write PB_CLK PB_BR[1] PB_BG[1] PB_ABB PB_TS PB_A[0:31] PB_AP[0:3] PB_TBST PB_TSIZ[0:3] PB_TT[0:4] 02 PB_AACK PB_ARTRY PB_DBG_IN PB_DBB PB_D[0:63] PB_DP[0:7] PB_DVAL PB_TA PB_TEA The following figures, single cycle write transfers on the PB Master Interface. Figure ...
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Processor Bus Interface Figure 16: PB Master Interface Single Cycle Write PB_CLK PB_BR[1] PB_BG[1] PB_ABB PB_TS PB_A[0:31] PB_AP[0:3] PB_TBST PB_TSIZ[0:3] PB_TT[0:4] PB_AACK PB_ARTRY PB_DBG_IN PB_DBB PB_D[0:63] PB_DP[0:7] PB_DVAL PB_TA PB_TEA 3.4.3.3 Data Alignment Embedded processor bus transfer sizes and ...
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Table 28: 64-bit PB Data Bus Byte Lane Definitions Byte Address 100 101 110 111 Table 29 lists the size and alignment transactions less than or equal to 8-bytes. The shaded table cells show transactions that support the PowerPC 7400 ...
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Processor Bus Interface Table 29: PowerSpan II Processor Bus Single Beat Data Transfers Size TSIZ[0:3] A[29:31] Tri-byte 0011 000 0011 001 0011 010 0011 011 0011 100 0011 101 Word 0100 000 0100 001 0100 010 0100 011 0100 ...
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PowerPC 7400 Transaction Support The PowerPC 7400 processors supports misaligned transactions within a double word (64-bit aligned) boundary. As long as the transaction does not cross the double word boundary, the PowerPC 7400 can transfer data on the misaligned address. ...
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Processor Bus Interface Table 30: PowerSpan II PB Data Parity Assignments Data Bus PB_D[24:31] PB_D[32:39] PB_D[40:47] PB_D[48:55] PB_D[56:63] The data parity bits, PB_DP[0:7], are driven to the correct values for even or odd parity by the PB Master during ...
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Errors The PB master detects three error conditions: • data parity on reads • assertion of PB_TEA_ by external slave • expiration of maximum retry counter (MAX_RETRY bit in the Miscellaneous Control and Status Register” on page See “Error ...
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Processor Bus Interface 136 PowerSpan II Bus Switch User Manual 80A1010_MA001_06 ...
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DMA A direct memory access (DMA) channel allows a transaction to occur between two devices without involving the host processor (for example, a read transaction between a peripheral device and host processor memory). Because less time is required to ...
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DMA There are two modes of operation for the PowerSpan II DMA: Direct mode and Linked-List mode. In Direct mode, the DMA control registers are directly programmed for each DMA transfer Linked-List mode, the PowerSpan II loads its DMA ...
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Most DMA channel registers are locked against any changes by the user while the channel is active. However, both the Stop Request (STOP_REQ) and Halt Request (HALT_REQ) bits, in the General Control and Status Register” on page 4.2.1.1 Source and ...
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DMA DMA Addresses and Retries If a PowerSpan II DMA transaction is retried enough times the its retry counter may expire. When the retry timer expires, the DMA transaction does not try to restart the transaction at the original ...
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Table 32: Programming Model for DMA General Control and Status Register Bits Type Description P1_ERR R/ A status bit indicating an error has occurred on PCI- 1. Write 1 to clear P2_ERR R/ A status bit indicating an error has ...
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DMA The default transfer type generated by the processor bus master is shown in Table 33. Table 33: Default PowerSpan II PB Master Transfer Type PB Master Transfer Writes Reads The Global (PB_GBL_) and Cache Inhibit (PB_CI_) parameters are ...
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The DMA channel delivers data from the source port to the destination port until: • DMA is stopped by setting the STOP_REQ bit • DMA encounters an error on one of the buses • transfer byte count decrements to zero ...
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DMA Figure 17: Direct Mode DMA Transfers Yes 144 Program: Source and destination addresses Transfer size and addresses Ensure status bits are clear Set GO bit Await termination of DMA Normal No Termination? Yes More transfers required? No Done ...
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Direct Mode Transfer Acknowledgment The following registers are updated during a transfer and can be used to monitor status during DMA channel activity: • DMA Source Address (DMAx_SRC_ADDR) in the Register” on page 367 • DMA Destination Address (DMAx_DST_ADDR) ...
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DMA Each command packet is 32-byte aligned. If the command packets are resident in PCI memory, the byte ordering is little-endian. If the command packets are resident in processor bus memory, the byte ordering is big-endian. command packets can ...
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Figure 18: DMA Command Packet Linked-List First Command Packet Address Offset: 0x00 Reserved 0x04 DMAx_SRC_ADDR 0x08 Reserved 0x0C DMAx_DST_ADDR 0x10 Reserved 0x14 DMAx_TCR 0x18 Reserved 0x1C DMAx_CPP 4.4.1 Initializing a Linked-List Mode Transfer A Linked-List mode DMA transfer is configured ...
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DMA Figure 19: Sequence of Operations in a Linked-List Transfer Set up Linked List in memory space Configure DMAx_ATTR Set DMAx_CPP [NCP] Set GO and CHAIN bit Await termination of DMA Termination? The DMA walks through the linked-list of ...
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Terminating Linked-List Mode Linked-List mode is terminated in two ways: setting the STOP_REQ bit or the HALT_REQ bit in the When the STOP_REQ bit is set, the DMA stops making source port requests. When all outstanding transactions are completed ...
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DMA 4.6 DMA Error Handling PowerSpan II can encounter external bus errors while mastering the source, destination or command packet ports on behalf of a DMA channel. Each DMA channel provides the following status bits in the Status Register” ...
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Destination Port Errors When an error occurs on the destination port transactions associated with any buffered data are terminated, and the appropriate DMAx_GCSR error bit is set. Due to the pipelined nature of DMA channel requests, additional destination port ...
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DMA 152 PowerSpan II Bus Switch User Manual 80A1010_MA001_06 ...
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I C/EEPROM 2 The I C (Inter-IC) bus is a bi-directional, two-wire serial data and serial clock bus that provides communication links between integrated circuits (ICs embedded application. Each device is recognized by a unique address ...
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I2C/EEPROM • Standard mode (up to 100 Kbits/s) • Single read/write (random read, byte write) • Sequential read during power-up configuration The interface consists of two pins: I2C_SDA and I2C_SCLK. I2C_SDA is a bidirectional open drain signal for transferring ...
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Table 36 defines the power-up EEPROM load sequence. The shaded areas indicate registers not visible in the Single PCI PowerSpan II. Table 36 tables for each of the registers listed in the table to obtain the corresponding PowerPC big-endian bit ...
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I2C/EEPROM Table 36: Power-up EEPROM Load Sequence Byte Offset Bit Name 0x09 7-0 P1_SID[SVID[15:8]] 0x0A 7-0 P1_SID[SVID[7:0]] 0x0B 7-2 1 P1_MISC1[INT_PIN[0]] 0 P2_MISC1[INT_PIN[0]] 0x0C 7-5 PowerSpan II Reserved 4 P1_MISC_CSR[BSREG_BAR_ EN] 3 P1_TI0_CTL[BAR_EN] 2 P1_TI1_CTL[BAR_EN] 1 P1_TI2_CTL[BAR_EN] 0 P1_TI3_CTL[BAR_EN] ...
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Table 36: Power-up EEPROM Load Sequence Byte Offset Bit Name 0x10 7 MISC_CSR[P1_LOCKOUT] 6 MISC_CSR[P2_LOCKOUT] 5-4 3 MISC_CSR[PCI_ARB_CFG] 2 MISC_CSR[PCI_M7] 1 MISC_CSR[PCI_M6] 0 MISC_CSR[PCI_M5] 0x11 7 IDR[P2_HW_DIR] 6 IDR[P1_HW_DIR] 5 IDR[INT5_HW_DIR] 4 IDR[INT4_HW_DIR] 3 IDR[INT3_HW_DIR] 2 IDR[INT2_HW_DIR] 1 IDR[INT1_HW_DIR] 0 ...
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I2C/EEPROM Table 36: Power-up EEPROM Load Sequence Byte Offset Bit Name 0x14 7-0 P2_SID[SID[15:8]] 0x15 7-0 P2_SID[SID[7:0]] 0x16 7-0 P2_SID[SVID[15:8]] 0x17 7-0 P2_SID[SVID[7:0]] 0x18 7-5 PowerSpan II Reserved 4 P2_MISC_CSR[BSREG_BAR_ EN] 3 P2_TI0_CTL[BAR_EN] 2 P2_TI1_CTL[BAR_EN] 1 P2_TI2_CTL[BAR_EN] 0 P2_TI3_CTL[BAR_EN] ...
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Table 36: Power-up EEPROM Load Sequence Byte Offset Bit Name 0x27 7-0 P1_CLASS[RID] 0x28 6 PB_SI0_CTL[TA_EN] 5 PB_SI0_CTL[MD_EN] 4-0 PB_SI0_CTL[BS] 0x29 7 PB_SI0_CTL[MODE] 6 PB_SI0_CTL[DEST] 5-0 0x2A 7 PB_SI0_CTL[PRKEEP] 6-5 PB_SI0_CTL[END] 4-3 2-0 PB_SI0_CTL[RD_AMT] 0x2B 7-0 PB_SI0_TADDR[31:24] 0x2C 7-0 PB_SI0_TADDR[23:16] ...
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I2C/EEPROM Table 36: Power-up EEPROM Load Sequence Byte Offset Bit Name 0x32 7-0 PB_REG_ADDR[23:16] 0x33 7-4 PB_REG_ADDR[15:12] 3-2 0 PB_REG_ADDR[END] 0x34 7-0 P2_ID[DID[15:8]] 0x35 7-0 P2_ID[DID[7:0]] 0x36 7-0 P2_ID[VID[15:8]] 0x37 7-0 P2_ID[VID[7:0]] 0x38 7-0 P2_CLASS[BASE] 0x39 7-0 P2_CLASS[SUB] 0x3A ...
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Bus Master master reads and writes can be performed from any one of the PowerSpan II’s three interfaces — accessing the “I2C/EEPROM Interface Control and Status Register” on page This register can be used to ...
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I2C/EEPROM There are four bits in and VPD_CS[2:0]. These bits may also be programmed in the Control and Status Register” on page When VPD_EN is set, PowerSpan II supports PCI Vital Product Data through the VPD capabilities registers in ...
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Arbitration Arbitration is a process used by multi-drop bus protocols, such as PCI, to support read and write access on a peripheral bus. A bus arbiter is a logic module that controls access to the bus by the devices ...
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Arbitration PowerSpan II provides external pins to support three additional external PCI masters PCI_REQ[7:5]#/PCI_GNT[7:5]#. Pairs of these additional arbitration — pins can be individually assigned to the PCI-1 arbiter or the PCI-2 arbiter (see Figure 20). Assignment of these ...
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Arbitration Levels The PowerSpan II PCI arbiter implements a fairness algorithm in order to prevent deadlocks. There are two priority levels signed to the PCI master agents. Fairness is defined by the PCI 2.2 Specification as an algorithm that ...
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Arbitration When a master takes longer than 16 clocks before starting a transaction, the STATUS bit is set the PCIx Arbiter Control register (see STATUS bit is set the PowerSpan II PCIx arbiter, ...
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Figure 21: Arbitration Algorithm Master B Master C Level 1 Level 0 Arbitration Order Level 1, Level 1, Level 1, Level 0 For example, if all bus masters assert Request ...
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Arbitration 6.2.2 Bus Parking The PowerSpan II PCI arbiter provides a flexible address bus parking scheme. When no master is requesting the address bus, the PCI arbiter can park on either the: • last bus master • specific bus ...
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PowerSpan II’s internal processor bus arbiter supports three external processor bus masters and implements internal request and grant lines for the PowerSpan II itself four processor bus masters in total. The external masters are enabled with the — External Master ...
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Arbitration 6.3.2 Data Bus Arbitration The arbiter samples PB_TT[3] when PB_TS_ is asserted to generate data bus requests. The arbiter grants the data bus to the current address bus owner by asserting one of PB_DBG[1:3]_ signals. The signal is ...
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Address Only Cycles The arbiter supports address only cycles. If Transfer Type (PB_TT[3]) is sampled low during PB_TS_, the arbiter does not grant the data bus. The use of PB_TT[ data bus request means that the PowerSpan ...
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Arbitration For more information on power-up options and boot selection, refer to II Power-up Options” on page 172 207. PowerSpan II Bus Switch User Manual “PowerSpan 80A1010_MA001_06 ...
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Interrupt Handling An interrupt is a signal informing a program that an event (for example, an error) has occurred. When a program receives an interrupt signal, it temporarily suspends normal processing and diverts the execution of instructions to a ...
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Interrupt Handling These classifications are discussed in the following sections. 7.2.1 Interrupts from Normal Operations Interrupt sources associated with normal device operations are: • Eight bidirectional, configurable interrupts pins: P1_INTA#, P2_INTA#, INT[5:0]_ • DMA channels (see • Doorbell interrupts ...
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P1_PB_RETRY • P1_P2_RETRY • P1_P1_ERR • P1_P1_RETRY 3. PCI-2 Interface errors • P2_PB_ERR • P2_P1_ERR • P2_A_PAR • P2_PB_RETRY • P2_P1_RETRY • P2_P2_ERR • P2_P2_RETRY See “Error Handling” on page 187 transaction exceptions are associated with error logging functionality. ...
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Interrupt Handling Table 38: Interrupt Register Description Register Type Register Description and Operation Mapping This series of registers allow each interrupt source to be mapped to a specific interrupt output pin. The mapping definitions are provided in “Interrupt Mapping” ...
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Interrupt Status When an interrupt source becomes active, the relevant status bit is set in one of the interrupt status registers. Interrupt Status is reported through two registers: “Interrupt Enable Register 0” on page 393 page 390. Interrupt Status ...
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Interrupt Handling Interrupt Status Register 1 provides status for interrupts resulting from exceptions occurring during device operation. This includes maximum retry errors, bus errors, and parity error. A register description for ISR1 is provided in Table 40: Register Description ...
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Table 40: Register Description for Interrupt Status Register 1 Bits Type Description P1_x_ERR R/ The PowerSpan II PCI-1 Interface detected an error. The corresponding PCI Control and Status Register must be checked for the error. Write 1 to Clear P1_A_PAR ...
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Interrupt Handling All interrupts are disabled by default. Table 41: Register Description for Interrupt Enable Register 0 Bits Type Description I2O_HOST_MASK R/W Masks an interrupt to the Host that there are outstanding MFAs in the Outbound Post List FIFO. ...
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Table 42: Register Description for Interrupt Enable Register 1 Bits Type Description P1_x_ERR_EN R/W Enables interrupt if the PowerSpan II PCI-1 Interface detected an error. The corresponding PCI Control and Status Register must be checked for the error. P1_A_PAR_EN R/W ...
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Interrupt Handling Each interrupt source contains a three bit field in an IMR_x register. This mapping field determines which external pin to assert when the source is active and enabled. Table 43 details the mapping scheme. The shaded area ...
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Interrupt Pins PowerSpan II has the following interrupt pins: • P1_INTA# • P2_INTA# • INT[5:0]_ Pins INT[5:0]_ are 5V tolerant and general purpose interrupt pins. Interrupt pins are active low and, when configured as input, are sampled on three ...
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Interrupt Handling 7.5 DMA Interrupts The PowerSpan II DMA supports a number of interrupt sources for each channel. Individual enable and status bits exist for each source. The status and enable bits are contained in the “DMA x General ...
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Mailboxes PowerSpan II provides eight 32-bit general Mailbox registers for passing messages between processes. Each Mailbox has an associated interrupt enable and status bit. When enabled, an interrupt is generated whenever there is a write to the Mailbox register. ...
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Interrupt Handling 186 PowerSpan II Bus Switch User Manual 80A1010_MA001_06 ...
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Error Handling Errors occur in a system as a result of parity, bus, or internal problems. In order to handle errors so that they have minimum effects on an application, devices have a logic module called an error handler. ...
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Error Handling • interrupt status bits in the is reported through PowerSpan II’s interrupt generation mechanisms • PCI standard error reporting mechanisms • error logging registers that capture parameters from the transaction that caused the error • assertion of ...
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Table 45 itemizes the error cases detected and reported by the PB master and the PB slave. Error logging in PB_ERRCS and PB_AERR is triggered for each of the error cases outlined in Table Table 45: PB Interface Errors Interface ...
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Error Handling Table 45: PB Interface Errors Interface Error Destination/Source PB Master Data parity External PCI-1 agent PB to PCI-1 DMA External PCI-2 agent PB to PCI-2 DMA DMA PB Linked-List DMA External agent External PCI-1 ...
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When a PowerSpan II PCI master is performing a read and encounters a Target- Abort, or generates a Master-Abort, an error indication is latched. When the Address Retry Enable (ARTRY_EN) bit, in the Control and Status Register” on page signaled ...
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Error Handling The transaction response for a PB slave error is as follows: • address parity: do not claim the transaction • data parity: transaction proceeds normally to its destination • illegal access (see The transaction response for a ...
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Standard PCI error reporting in page 301 (Px_CSR). • Capture of specific parameters from the transaction that caused the error: Error Control and Status register Px_ERRCS, which logs PCI command Address Error Log register Px_AERR, which logs PCI Address ...
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Error Handling Table 46: PCI Interface Errors Destination/ Interface Error Source Px Address PB, Registers, Py parity target Data parity PB, Registers Py Propagation PB of error from destination master Py 194 Conditions Reporting Write, Read Px_SERR if PERESP=1 ...
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Table 46: PCI Interface Errors Destination/ Interface Error Source Px Data parity External PB agent master DMA External Py agent DMA DMA Px Linked-List DMA External External PB agent agent Px ...
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Error Handling Table 46: PCI Interface Errors Destination/ Interface Error Source Px Px master External PB agent master generates DMA Master-Abort DMA External Py agent DMA DMA ...
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The shaded row from the Px master section of sets the Px_PB_ERR bit in the ISR1 register and the R_TA bit in the Px_CSR register if its transaction terminates with a Target-Abort. The sources for such a transaction are: • ...
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Error Handling The transaction response for a Px target error is: • address parity: claim and complete as normal • data parity: transaction proceeds normally to its destination The transaction response for a Px master error is: • data ...
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Assume that an error occurred at the PCI-1 master using DMA-2. A typical interrupt service routine executes the following steps: 1. ISR1 read to determine which interface reported the error PCI-1 reports the error: • error logs P1_ERRCS ...