PCI6150-BB66PC PLX Technology, Inc., PCI6150-BB66PC Datasheet

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PCI6150-BB66PC

Manufacturer Part Number
PCI6150-BB66PC
Description
PCI-to-PCI Bridge
Manufacturer
PLX Technology, Inc.
Datasheet

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PCI 6150 (HB4)
PCI-to-PCI Bridge
Data Book

PCI6150-BB66PC Summary of contents

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PCI 6150 (HB4) PCI-to-PCI Bridge Data Book ...

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...

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PCI 6150 (HB4) PCI-to-PCI Bridge Data Book Version 2.0 May 2003 Website: http://www.plxtech.com Technical Support: http://www.plxtech.com/support Phone: 408 774-9060 800 759-3735 Fax: 408 774-2169 ...

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... PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products ...

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... Supports out of order delayed transactions PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. PCI 6150 PCI-to-PCI Bridge CPCI Hot Swap Specification PICMG 2.1 R2.0 with support Device Hiding support eliminates mid- ...

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... Removed Section 6.3.3, Extended Registers Updated Configuration Map in Section 6.1 to reflect deletion of Extended Registers Updated Register DEh, bits 15-11 Added three notes to table in Section 14.5, Frequency Division Options Updated Section 20.3.1, 24-3Fh PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Eng Chk Mkt Chk 6 ...

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... Delayed Read Completion with Target............................................................................................... 63 7.5.12 Delayed Read Completion on Initiator Bus ........................................................................................ 64 7.5.13 Configuration Transactions ................................................................................................................ 64 7.5.14 Type-0 Access to PCI 6150................................................................................................................ 65 7.5.15 Type-1 to Type-0 Translation ............................................................................................................. 65 7.5.16 Type-1 to Type-1 Forwarding ............................................................................................................. 66 7.5.17 Special Cycles .................................................................................................................................... 67 PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. .............................................................................................................. 13 S ............................................................................................................... 15 IGNALS S .......................................................................................................... 17 IGNALS ............................................................................................................................ 19 ............................................................................................................................ 20 S ............................................................................................... 21 NTERFACE IGNALS ...

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... CLOCKS ....................................................................................................................................................... 94 14 RIMARY AND ECONDARY 14 ECONDARY LOCK UTPUTS 14 ISABLING NUSED ECONDARY 14.3.1 Secondary Clock Control.................................................................................................................... 94 PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. ........................................................................................................................ 67 ..................................................................................................................... 74 ............................................................................................................................. 77 ........................................................................................................................... 80 S ................................................................................................ 84 UMMARY ......................................................................................................... 87 EPORTING A PCI 6150...................................................................................... 88 CROSS ........................................................................................................................ 89 .................................................................................................................. 90 ............................................................................................................. 90 ........................................................................................................................ .................................................................................................... 94 LOCK NPUTS ...................................................................................................................... ...

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... ATINGS 25 UNCTIONAL PERATING 25 LECTRICAL HARACTERISTICS 25.4 PCI IGNAL IMING PECIFICATION 25.4.1 PCI Signal Timing............................................................................................................................. 115 PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. S ........................................................................................................... 95 OURCE .................................................................................................................... ........................................................................... 96 ASTER THAN RIMARY ORT ........................................................................................................................ 98 R ....................................................................................................... 99 ESET ( ........................................................................... 100 NITIATED BY RIDGE ASTER ...

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... PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 10 ...

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... Non-transparent, Primary .......................................... 54, 56, 57 P_SERR_L Event Disable Register ...........................................49 P_SERR_L Status Register .......................................................52 PMCSR Bridge Support Non-transparent, Primary ......................................................55 PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Power Management Capabilities Non-transparent, Primary...................................................... 54 Power Management Control/ Status Non-transparent, Primary...................................................... 55 Prefetchable Memory Base Register ......................................... 35 Prefetchable Memory Base Register Upper 32 Bits ...

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... Ordering Information Part Number Rev. Description PCI 6150 BA 32-bit PCI-to-PCI bridge PCI 6150 BB 32-bit PCI-to-PCI bridge PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 12 ...

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... PCI devices. This clock can be asynchronous and need not be at the same frequency as the host system PCI clock input. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Secondary Bus PCI devices S-PORT PCI 6150 P-PORT Host System Back-Plane ...

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... PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. PCI 6150 TOP VIEW 156 155 154 ...

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... Once asserted in a data phase not deasserted until end of the data phase. Before being three-stated driven to a deasserted state for one cycle. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 15 ...

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... P_PAR to valid logic level. P_M66EN PI Primary 66 MHz Enable: Set high for 66MHz primary bus. This signal, along with the S_M66EN signal, controls the frequency output to the SCLKOUT pins. See Chapter 15 for more details. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 16 ...

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... Before being three-stated driven to a deasserted state for one cycle. S_SERR# PI Secondary System Error: Can be driven LOW by any device to indicate a system error condition. This signal should be pulled up through an external resistor. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 17 ...

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... This signal, along with the P_M66EN signal, controls the frequency output to the S_CLKOUTn pins. This pin should be pulled High or Low externally. See Chapter 15 for more details PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 18 ...

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... When asserted, all primary PCI signals are three-stated and no bus parking is asserted. S_RSTOUT# PO Secondary Reset Output: Asserted when any of the following conditions is met: 1. Signal P_RSTIN# is asserted. 2. The Secondary reset bit in the bridge control register (Register 3Eh) in configuration space is set. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 19 ...

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... Secondary Interface I/O Voltage This signal must be tied to either 3.3V or 5V, depending on the signaling voltage of the secondary interface. Pin 151 PCI 6150 does not use this pin. Reserved PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. REQ# output to External Arbiter. 20 ...

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... Test Reset: It provides an asynchronous initialization of the TAP controller. This pin MUST be pulled high or pulled low to a known state using an external resistor. We recommend pulling low using a 330ohm resistor. 5.8 Power Signals Name Type Description VDD +3.3V GND Ground PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 21 ...

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... TS 16 S_GNT6 S_GNT7 S_GNT8 VSS P 20 S_CLK I 21 S_RST S_CFN PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Signal Type PIN Name NO. S_CLKOUT5 O 36 VSS S_CLKOUT6 O S_CLKOUT7 O 39 VDD P 40 S_CLKOUT8 O 41 ...

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... TS 28 S_CLKOUT0 O 29 S_CLKOUT1 O 30 VSS P 31 S_CLKOUT2 O 32 S_CLKOUT3 O 33 VDD P 34 S_CLKOUT4 O 35 PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. VSS P 59 P_AD26 TS 60 P_AD25 TS 61 VDD P_AD24 TS 64 P_CBE3# TS P_IDSEL I 65 VSS P 66 ...

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... P_VIO I 124 CFG66 I 125 MSK_IN I 126 PIN_ENUM# O 127 PIN_LED I/O 128 TDI I 129 PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Signal Type PIN Name NO. 141 S_AD3 TS 142 VSS P 143 S_AD4 TS 144 S_AD5 TS 145 VDD P 146 S_AD6 TS 147 S_AD7 ...

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... VSS P 136 S_AD0 TS 137 S_AD1 TS 138 VDD P 139 S_AD2 TS 140 PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 165 S_AD15 TS 166 VSS P 167 S_CBE1# TS 168 S_PAR TS 169 S_SERR# I 170 VDD P 171 S_PERR# STS 172 S_LOCK# STS 173 S_STOP# ...

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... P_AD2 TS 119 P_AD3 TS 118 P_AD4 TS 116 P_AD5 TS 115 P_AD6 TS 113 P_AD7 TS 112 P_AD8 TS 109 PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Signal Type PIN Name NO. P_AD21 TS 70 P_AD22 TS 68 P_AD23 TS 67 P_AD24 TS 63 P_AD25 TS 61 P_AD26 TS ...

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... P_AD14 TS 95 P_AD15 TS 93 P_AD16 TS 77 P_AD17 TS 76 P_AD18 TS 74 P_AD19 TS 73 P_AD20 TS 71 PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. P_PAR TS 90 P_PERR# STS 88 P_REQ P_RST P_SERR P_STOP# STS 85 P_TRDY# STS 83 P_VIO 124 ...

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... TS 14 S_GNT4 S_GNT5 S_GNT6 S_GNT7 S_GNT8 S_IRDY# STS 177 PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Signal Type PIN Name NO. S_REQ7 S_REQ8 S_RST S_SERR# I 169 S_STOP# STS 173 S_TRDY# ...

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... S_REQ0# I 207 S_REQ1 S_REQ2 S_REQ3 S_REQ4 S_REQ5 S_REQ6 PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. VDD P 105 VDD P 108 VDD P 114 VDD P 120 VDD P 131 VDD P 139 VDD P 145 VDD ...

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... Incremental Prefetch Count Prefetch Count 2 Reserved Secondary Flow Through Control Reserved Test register EEPROM Data PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Bits 15-8 1,2 Vendor ID Primary Command Primary Latency Cache Line Size Timer Reserved Secondary Bus Primary Bus ...

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... Power Management Capabilities 1,2 Power PMCSR Bridge Management Data Support Reserved HSCSR = 00 VPD Register = 0000 VPD Data Register = 0000_0000 PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Reserved GPIO[3-0] Output P_SERR# event Data Clock Control Reserved Reserved ROR control Reserved Reserved ...

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... Fast Back to R/W Back Enable 10-15 Reserved R/O PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description Controls the bridge’s response to I/O accesses on the primary interface. 0=ignore I/O transaction 1=enable response to I/O transaction Reset to 0. Controls the bridge’s response to memory accesses on the primary interface ...

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... Programmed with the number of the PCI bus to which the secondary bridge interface is connected. This value is set with configuration software. Reset to 0. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description Reserved (set to ‘0’s). Enhanced Capabilities port. Reads indicate PCI 6150 supports an enhanced capabilities list ...

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... System Error 15 Detected R/WC Parity Error PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description Reserved (set to ‘0’s). Defaults to 1. PCI 6150 is 66Mhz Capable. No User-Definable Features (set to ‘0’). Fast back-to-back write capable on secondary port (set to ‘1’). ...

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... Interrupt Pin Register (Read Only) – Offset 3Dh Reads indicate that PCI 6150 does not use any interrupt pin. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description Enhanced capabilities port offset pointer. This register reads as DCh to indicate the offset of the power management registers ...

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... Master Abort R/W Mode PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description Controls the bridge’s response to parity errors on the secondary interface. 0=ignore address and data parity errors on the secondary interface 1=enable parity error reporting and detection on the secondary interface Reset to 0 ...

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... P_SERR# enable 15-12 reserved R/O PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Forces the assertion of S_RSTOUT# signal pin on the secondary interface. 0=do not force the assertion of S_RSTOUT# pin 1=force the assertion of S_RSTOUT# pin Reset fast back to back transaction 1= reserved ...

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... R/O PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description Controls when the chip as a target disconnects memory transactions. When 0, disconnects on queue full 4KB boundary. When 1, disconnects on a cache line boundary, as well as when the queue fills boundary. Reset value is 0. ...

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... Reserved R/O PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description Maximum number of clocks that PCI 6150 will wait for posted write data from initiator if delivering write data in flow through mode and internal post write queues are almost empty. If the count is exceeded without any additional data from the initiator, the cycle to target will be terminated to be completed later ...

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... R/W master timeout divider PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description Controls maximum number of times that PCI 6150 will retry a cycle before signaling a timeout. This timeout applies to Read/Write retries and can be enabled to trigger SERR# on the primary or secondary port depending the SERR# events that are enabled ...

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... Reserved R/O PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description If 1, PCI 6150 will always wait for PERR# status of the target before completing a delayed write transaction to the initiator. Defaults PCI 6150 will always wait for PAR status of the target before completing a delayed read transaction to the initiator ...

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... Reserved R/O PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved PCI 6150 will pass memory write and invalidate commands if there is at least 1 cache line of FIFO space available, otherwise it will complete as a memory write cycle PCI 6150 will retry memory write and invalidate commands if there is no space for 1 cache line of data in the internal queues ...

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... Reserved R/O PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description Controls initial prefetch count on the Primary bus during reads to prefetchable memory space. This register value should be a power of 2 (only one bit should be set any time). Value is number of double words ...

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... Reserved R/O PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description This controls incremental read prefetch count. When an entry’s remaining prefetch Dword count falls below this value, the bridge will prefetch an additional “Secondary incremental prefetch count” ...

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... Reserved R/O PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description Maximum number of clocks that PCI 6150 will wait for posted write data from initiator if delivering write data in flow through mode and internal post write queues are almost empty. If exceeded without any additional data from the initiator, the cycle to target will be terminated completed later ...

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... R/W priority master in high priority group PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description If 1, the low priority group uses the fixed priority arbitration scheme, otherwise a rotating priority arbitration scheme is used Defaults to 0 This bit is only valid when the low priority arbitration group is set to a fixed arbitration scheme ...

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... R/O autoload status 3-7 Reserved R/O PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Controls bus grant behavior during idle. 0000 : Last master granted is parked 0001 : Master #0 is parked … 1001 : Master #8 is parked 1010 : PCI 6150 is parked other : grant is deasserted ...

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... Function Type 15-0 EEPROM R/W Data PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description Starts the EEPROM read or write cycle. Controls the command sent to the EEPROM 1 : write 0 : read This bit is set EEPROM ACK was not received during EEPROM cycle. ...

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... Reserved R/O PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description Reserved. Returns 0 when read Controls ability of PCI 6150 to assert P_SERR# when a data parity error is detected on the target bus during a posted write transaction. P_SERR# is asserted if this event occurs when this bit is 0 and SERR# enable bit in the command register is set ...

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... GPIO[3:0] R/O input data PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description Writing 1 to any of these bits drives the corresponding bit low on the GPIO[3:0] bus programmed as output. Writing 0 has no effect. Read returns the last written value. Resets to 0. ...

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... Clock 7 R/W Disable PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description If either bit is 0, S_CLKOUT[0] is enabled. When both bits are 1, S_CLKOUT[0] is disabled. Upon secondary bus reset, this bit is initialized by shifting in a serial data stream. These bits are assigned to correspond to the PRSNT# pins for slot 0 ...

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... Delayed R/WC transaction master timeout PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved S_CLKO[8] is enabled. When 1, S_CLKO[8] is disabled. Upon secondary bus reset, this bit is initialized by shifting in a serial data stream S_CLKO[9] is enabled. When 1, S_CLKO[9] is disabled. Upon secondary bus reset, this bit is initialized by shifting in a serial data stream ...

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... R/W 7 ROR Write Enable PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description Reserved Read Only Registers Write Enable: Subsystem Vender ID at Register 2Ch and Subsystem ID Register at 2Eh are normally Read Only. Setting this bit to 1 will enable write to such Read Only ID Registers. ...

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... PME Support R/O PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description This register is set to 001b, indicating that this function complies with Rev 1.0 of the PCI Power Management Interface Specification This bit is a '0', indicating that PCI 6150 does not support PME# signaling. This bit is set to ‘ ...

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... Power Management Data Register (RO) – Offset E3h This register is EEPROM or ROR Write controlled loadable, but is READ ONLY during normal operation. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state ...

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... R/W1C Insertion State 15:8 Reserved R/O PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description Device Hiding Arm. Reset Arm Device Hiding 0 = Disarm Device Hiding DHA is set hardware during hot swap port PCI RSTIN# going inactive and handle switch is still unlocked. The locking of the handle will clear this bit ...

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... Type 31-0 VPD Data R/W PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Description Reserved VPD operation: Writing a ‘0’ to this bit generates a read cycle from the EEPROM at the VPD address specified in bits 7-2 of this register. This bit will remain at a logic ‘0’ value until EEPROM cycle is finished, then it be set to ‘ ...

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... PCI 6150 supports the linear increment address mode only, which is indicated when the low 2 address bits are equal either of the low 2 address bits is nonzero, PCI 6150 automatically disconnects the transaction after the first data transfer. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Initiates as Master Responds as Target Primary ...

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... The posted write data buffer fills When one of the last two events occurs, PCI 6150 returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Type of Forwarding Posted Posted ...

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... PCI 6150 claims the access returns TRDY# to the initiator, to indicate that the write data was transferred. If the initiator requests multiple QUAD/DWORD, PCI 6150 asserts STOP# in conjunction with TRDY# to signal a PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 24 attempts (programmable through register 45, bits 3-0), PCI 6150 ceases ...

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... Delayed write transactions are posted as long as at least one open entry in the delayed transaction queue exists. PCI 6150 can queue up to four posted write transactions and four delayed transactions in both upstream and downstream directions. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Condition Aligned Address Boundary All ...

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... If these locations are mapped in memory space, use the memory read command and map the target into nonprefetchable (memory-mapped I/O) memory space to utilize nonprefetching behavior. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 62 ...

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... If the transaction is terminated via normal master termination or target disconnect after at least one data transfer has been completed, PCI 6150 does not initiate any further attempts to read more data. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Address space Prefetch aligned address boundary - ...

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... Type-1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle generated on another PCI bus. A Type-1 configuration command is identified by the configuration command and the Lowest 2 address bits set to 01b. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 24 attempts (default), PCI 6150 ceases further read 64 ...

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... PCI 6150 asserts a unique address line based on the device number. These address lines may be used as secondary bus IDSEL signals. The mapping of the address lines depends on the device number in the Type-1 address bits P_AD[15:11]. Table 8–6 presents the mapping that PCI 6150 uses. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 65 ...

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... The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. The bus command is a Configuration Read or Write transaction. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Secondary IDSEL S_AD[31:16] 00000 0000 0000 0000 0001 ...

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... IRDY# on the following cycle. IRDY# must be asserted in the same cycle in which FRAME# deasserts. If FRAME# is already deasserted, IRDY# can be deasserted on the next clock cycle following detection of the master abort condition. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 67 ...

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... P_SERR# if enabled by the SERR# enable bit in the command register and if not disabled by the device-specific P_SERR# disable bit for master abort during posted write transactions (that is, master abort mode = 1; SERR# enable bit = 1; and P_SERR# disable bit for master aborts = 0. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 68 ...

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... Normal Target retry Target disconnect Target abort PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Response Return disconnect to initiator with first data transfer only if multiple data phases requested. Return target retry to initiator. Continue write attempts to target. Return disconnect to initiator with first data transfer only if multiple data phases requested ...

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... PCI 6150 returns a target abort. 7.6.4 Target Termination Initiated by PCI 6150 PCI 6150 can return a Target Retry, Target Disconnect, or Target-Abort to an initiator for reasons other than detection of that condition at the target interface. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 70 ...

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... PCI 6150 is unable to obtain delayed read data from the target or to deliver delayed write data to the 24 target after 2 attempts. When PCI 6150 returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 71 ...

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... When the I/O range is turned off, all I/O transactions are forwarded upstream, and no I/O transactions are forwarded downstream. The I/O range has a minimum granularity of 4KB and is aligned on a 4KB boundary. The maximum I/O range is 4GB in size. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 72 ...

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... When the ISA enable bit is set, devices downstream of PCI 6150 can have I/O space mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the 64KB boundary. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 73 ...

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... Write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. To turn off the memory-mapped I/O address range, write the memory-mapped I/O base address register with a value greater than that of the memory-mapped I/O limit address register. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 74 ...

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... PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 64 bytes when 64-bit addressing is used. ...

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... I/O space. Note If both the VGA mode bit and the VGA snoop bit are set, PCI 6150 behaves in the same way as if only the VGA mode bit were set. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 76 ...

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... If more than one delayed transaction is initiated, the initiator should repeat all the delayed transaction requests, PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 77 ...

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... The read transaction can be to the same location as the write data the read transaction were to pass the write transaction, it would return stale data. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Delayed Write Request Request ...

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... Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written (or some other location along the same path), or from the device driver to one of the device registers. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 79 ...

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... If the parity error response bit is not set, PCI 6150 does not assert P_PERR#. PCI 6150 sets the detected parity error bit in the status register, regardless of the state of the parity error response bit. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 80 ...

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... In this case, a master timeout condition may occur, possibly resulting in a system error (P_SERR# assertion). PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 81 ...

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... PCI 6150 asserts S_PERR# two cycles after the data transfer, if both of the following are true: The primary interface parity error response bit is set in the command register. The secondary interface parity error response bit is set in the bridge control register. PCI 6150 completes the transaction normally. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 82 ...

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... Because the data has already been delivered with no errors, there is no other way to signal this information back to the initiator. If the parity error was forwarded from the initiating bus to the target bus, P_SERR# is not asserted. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 83 ...

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... The parity error response bit in the command register, corresponding to the primary interface, must be set. The P_PERR# signal is detected asserted or a parity error is detected on the primary bus. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Direction Bus where error ...

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... Posted write 0 Delayed write 1 Delayed write 0 Delayed write 0 Delayed write 1 x =don’t care PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Direction Bus where error was detected Downstream Primary Downstream Secondary Upstream Primary Upstream Secondary Downstream Primary ...

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... Delayed write 1 x =don’t care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Direction Bus where error was detected Downstream Primary Downstream ...

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... P_SERR# assertion for specific events. The master timeout condition has a SERR# enable bit for that event in the bridge control register and therefore does not have a device-specific disable bit. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Direction Bus where error ...

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... If the LOCK# sequence is not used in subsequent attempts, a master timeout condition may result. When a master timeout condition occurs, SERR# is conditionally asserted, the read data and queued read transaction are discarded, and the LOCK# signal is deasserted on the target bus. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 88 ...

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... Signal SERR# is asserted for the master abort condition if the master abort mode bit is set in the bridge control register. Note: PCI 6150 has an option to ignore the lock protocol, through register 46h, bits 13 and 14. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 89 ...

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... Each master can be assigned to either the low priority group or the high priority group, through configuration register 42h. Each group can be programmed to use a rotating priority or a fixed priority scheme, through configuration register 50h. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 90 ...

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... Priority is also re-evaluated if the requesting agent deasserts its request without generating any cycles while it was granted. If PCI 6150 detects that an initiator has failed to assert S_FRAME# after 16 cycles of both grant assertion and a secondary idle bus condition, the arbiter will re-evaluate grant assignment. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. lpg ...

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... Last master granted: grant is assign to the last granted master. These options are selected through Internal Arbiter Control register at 50h, bits 12-15. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. B, m0, m1, m2, m7, m8, m3, m4, m5 m2, m1, m0, m7, m6, m5, m4, m3, m8 ...

Page 93

... GPIO output is driven low. Writing zeros to these registers has no effect. The value written to the output register will be driven only when the GPIO signal is configured as output. Type-0 configuration write operation is used to program these fields. The reset value for the output is 0. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 93 ...

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... PCI 6150. The shift registers can be eliminated, and MSKIN can be tied low to enable all secondary clock outputs or tied high to force all secondary clock outputs high. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 94 ...

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... PCI 6150 also has S_CLK_STB input allowing designer to indicate the Secondary external clock source is stable. If this input is 0 indicating that the S_CLKIN is not yet stable, the PCI 6150 will not let S_RSTOUT# deassert. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. SCLK_O OUTPUT 0 ...

Page 96

... SCLKn outputs, the division control can be disabled by pulling the S_M66EN pin HIGH and not connecting this pin to the PCI slots. Otherwise external clock can be fed directly into the S_CLKIN. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 1/1 1/2 ...

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... When OSCIN or other external clock inputs are used for the secondary port, PCI 6150 can run with a maximum ratio of 1:2.5 or 2.5:1 between primary and secondary bus clocks. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 97 ...

Page 98

... P_RSTIN# is deasserted, or while the secondary clock serial disable mask is being shifted in (16 clock cycles after P_RSTIN# deassertion). The Secondary Reset bit in the bridge control register is set. Signal S_RSTOUT# remains asserted until the rest control bit is cleared. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 98 ...

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... Reset Inputs P_RSTIN# S_RSTOUT# Register 41h bit 0 Chip Reset Register 3Eh bit 6 Secondary Reset PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Transparent Mode - Resets Primary and Secondary Ports - Causes S_RSTOUT# active - Causes EEPROM load - Not used as input ...

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... Master abort indicates that PCI 6150 acting as a master receives no response (i.e., no target asserts P_DEVSEL# or S_DEVSEL#) from a target. the bridge deasserts FRAME# and then deasserts IRDY#. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Target PCI 6150 does not respond. It detects this situation by ...

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... PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. S_AD[31:16] Device Number 0000 0000 0000 0001b 0 (Source Bridge) 0000 0000 0000 0010b 0000 0000 0000 0100b … 0000 1000 0000 0000b 0001 0000 0000 0000b … ...

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... Otherwise, when MPC has been reached, the PCI 6150 will not prefetch any more. The incremental prefetch can be disabled by setting IPC >= MPC. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 102 ...

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... PCI 6150 will first prefetch 10H (20H-10H) count and then continues to prefetch another 20H count. Afterwards, incremental prefetch is invoked until the Maximum Prefetch count is reached, or flow through is achieved. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 103 ...

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... Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to ensure the machine is in RESET state at power-up. PCI 6150 implements 3 basic instructions: BYPASS, SAMPLE/PRELOAD, and EXTEST. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 104 ...

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... Before the PCI 6150 registers can be accessed through host, user should check the auto-load condition by reading the EEPAUTO bit. Host access is allowed only after EEPAUTO status becomes '0' which means that the autoload initialization sequence is complete. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 105 ...

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... Read Device Address Address ( PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved ord C C Data ( ord ...

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... End of Group 3 24-3Fh Reserved (Must be set to 0) PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 0001 = stop autoload at offset 13h: Group 2 0011 = stop autoload at offset 23h: Group 3 0111 = stop autoload at offset 27h: Group 4 1111 = autoload all EEPROM loadable registers: Group 5 ...

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... PCI 6150 provides for storage of 192 bytes of VPD data in the EEPROM device. VPD related registers are located starting at offset ECh of the PCI configuration space. VPD also uses the enhanced capabilities port address mechanism. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 108 ...

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... PCI 6150 to D0. Power-up reset. The PCI 6150 performs the standard power-up reset D3 D0 functions. cold PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. power management states cold and D3 power management states for devices behind the bridge hot cold ...

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... If PCI 6150 is not participating in a transaction when Device Hiding is invoked, PCI 6150 shall not respond as a target to any subsequent transactions until Device Hiding is canceled. Device Hiding is cancelled when the handle switch is relocked. PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. 110 ...

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... PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 ...

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... W1 W2 Package width (length) W3 Package overall width (length) P1 Lead pitch P2 Lead width C Lead thickness D H1 Package overall height H2 Package thickness L Lead length F Foot length N Foot angle PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Minimum Nominal 27.95 28.00 30.60 0.50 0.17 0.09 0.13 4.20 3.17 1.30 0.45 0.60 0 Maximum 28.05 0.27 0.20 3.95 0.75 7 112 ...

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... Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. 25.2 Functional Operating Range Parameter Supply Voltage Operating ambient temperature PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Minimum Maximum -55 °C 125 °C 125 °C 3.9V 5 ...

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... V Input LOW Voltage il V Output LOW Voltage ol V Output HIGH Voltage oh I Input Leakage Current il C Input Pin Capacitance in PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Condition Min 3.0 3 1500 A iout 0 -500 A DD iout 0 < V < ...

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... Active to float delay off T Input setup time to CLK – su bused signals T Input setup time to CLK – su(ptp) point to point T Input signal hold time from h CLK PCI 6150 Data Book v2.0 2003 PLX Technology, Inc. All rights reserved. Minimum Maximum Unit ...

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