MSM548263-60JS Oki Semiconductor, MSM548263-60JS Datasheet
MSM548263-60JS
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MSM548263-60JS Summary of contents
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... MSM548263 262,144-Word ¥ 8-Bit Multiport DRAM DESCRIPTION The MSM548263 is a 2-Mbit CMOS multiport DRAM composed of a 262,144-word by 8-bit dynamic RAM, and a 512-word by 8-bit SAM. Its RAM and SAM operate independently and asynchronously. It supports three types of operations: random access to RAM port, high speed serial access to SAM port, and bidirectional transfer of data between any selected row in the RAM port and the SAM port ...
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... A0 25 44/40-Pin Plastic TSOP (II Pin Name SC SE DSF QSF pin. SS MSM548263 SDQ8 42 SDQ7 41 SDQ6 40 SDQ5 DQ8 37 DQ7 36 DQ6 35 DQ5 DSF CAS 28 QSF Type) ...
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Column Address Column Decoder Buffer Sense Amp. Row 512 ¥ 512 ¥ 8 Address RAM ARRAY Buffer Refresh Gate Counter SAM Serial Decoder SAM SAM Address Address Counter Buffer SAM Stop Control Block Write Column Mask Control ...
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... 2 £ V £ All other pins not LI under test = £ V £ 5.5 V OUT I LO Output Disable MSM548263 (Note: 1) Rating Unit –1 °C –55 to 150 °C (Ta = 0°C to 70°C) (Note: 2) Max. Unit 5.5 V 6.5 V ...
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... CC5 min.) Active I RC CC5 Standby I CC6 Active I CC6 Standby I CC7 Active I CC7 Standby I CC8 Active I CC8 MSM548263 ( ±10 0°C to 70°C) CC -60 -70 -80 Unit Note Max. Max. Max 140 130 120 ...
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... WCH t 50 — 55 — WCR t 10 — 12 — — 20 — RWL t 15 — 20 — CWL MSM548263 -80 Unit Note Max. — ns — — — ns — — — — ...
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... TRP t 20 — 20 — — 70 — RSD t 40 — 45 — ASD t 20 — 20 — CSD t 5 — 5 — TSL MSM548263 -80 Unit Note Max. 0 — — — ns — — — — — ns — ...
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... SZE t 0 — 0 — SZS t 0 — 0 — SWS t 10 — 10 — SWH t 0 — 0 — SWIS t 10 — 10 — SWIH MSM548263 -80 Unit Note Max. 15 — — — — — ns — — — ...
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... AWD (Max.) limit ensures that t RCD (Max.) limit ensures that t RAD RAD / SOH COH SCA MSM548263 and (Min.), t t RWD RWD CWD CWD (Max.) can be met. RAC is greater than the specified RCD ...
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... Open DQ1 - THS THH TRG RAS t CSH t RSH t CAS t RAL t t ASC CAH Column t FHR t t FSC CFH t RCS t CAC RAC t AA Valid Data t ROH t OEA MSM548263 CRL t RCH t RRH t OFF t OEZ "H" or "L" 10/40 ...
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... Open DQ1 - THS THH TRG RAS t CSH t RSH t CAS t RAL t t ASC CAH Column t FHR t t FSC CFH t RCS t CAC RAC t AA Valid Data t ROH t OEA MSM548263 RCL t RCH t RRH t OFF t OEZ "H" or "L" 11/40 ...
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... FSC CFH FSC CFH t RCS t t RCS RCH t t CAC CAC t t COH AA Valid Data t RAC CPA t OEA MSM548263 t RSH CAS CP CAS t RAL t t ASC CAH Column t t FSC CFH t t RCH RCS t t RRH RCH t CAC t ...
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... Masked Write (New/Old) 1 Column Mask Masked Block Write (New/Old Masked Flash Write (New/Old) 0 Valid Data Normal Write 1 Column Mask Block Write 0 Write Mask Data Load Mask Register 1 Color Data Load Color Register Column Mask Data Low: Mask High: No Mask MSM548263 Function 13/40 ...
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... RWH WCR DQ1 - THS THH TRG RAS t CSH t RSH t CAS t RAL t t ASC CAH Column t FHR t t FSC CFH B t CWL t RWL WCS WCH t DHR MSM548263 t RP "H" or "L" 14/40 ...
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... WSR RWH DQ1 - THS TRG RAS t CSH t RSH t CAS t RAL t t ASC CAH Column t FHR t t FSC CFH B t CWL t t RCS RWL WCR t DHR OEH MSM548263 t RP "H" or "L" 15/40 ...
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... RWC t RAS t CSH t RSH t CAS t RAL t t ASC CAH Column t AWD FHR t t FSC CFH B t CWL RCS CWD RWL CAC t RWD t RAC DZC DS DH Valid E Data t DZO OEZ OEA OEH MSM548263 "H" or "L" 16/40 ...
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... CAH Column Column CFH FSC CFH CWL CWL WCS WCH WCH MSM548263 RSH CAS t RAL t t ASC CAH Column t t FSC CFH B t CWL t t WCS WCH ...
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... CWD CWD CAC CAC Out In Out OEZ OEZ t t OEA OEA MSM548263 RSH CAS t RAL t t ASC CAH Column t t FSC CFH B t CWL t AWD t CWD CAC ...
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... Semiconductor RAS Only Refresh Cycle RAS t CRP CAS t t ASR RAH Address Row t t FSR RFH DSF WE DQ1 - THS THH TRG RAS Open MSM548263 RPC "H" or "L" 19/40 ...
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... CHR Inhibit Falling Transition t RAH A t RFH RWH C Open CBR Cycle Function Table CBR Refresh (Reset All Options CBR Refresh (Set STOP Address CBR Refresh (No Reset Options) MSM548263 RPC "H" or "L" Function 20/40 ...
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... RAS RSH t RAL t t ASR t ASC CAH Column t FHR t FSR t t FSC CFH t WSR t t RRH RCS t CAC RAC t OEA MSM548263 t RAS t CHR t RAH A t RFH B t RWH C t OFF Valid Data t OEZ "H" or "L" 21/40 ...
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... QSF = "H"-- Upper SAM (256 - 511) is active RAS t CSH t RSH t CAS t RAL t t ASC CAH SAM Start t ASD t CSD Open t RSD TSD t SCP Note 2 t SZS t TQD t CQD Note 3 MSM548263 TRP t SCC SCA t t SCA SOH Data Out Note 3 "H" or "L" 22/40 ...
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... QSF = "H"-- Upper SAM (256 - 511) is active RAS t CSH t RSH t CAS t RAL t t ASC CAH SAM Start t CTH t ATH Open RTH t t TSL TSD Data Out Data Out t TQD Note 2 MSM548263 TRP t SCA t SOH Data Out Note 2 "H" or "L" 23/40 ...
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... CSH t RSH t CAS t RAL t t ASC CAH SAM Start Sj t CTH t ATH Open t RTH t SCC t t SCP STOP SCA t SOH Data Out Data Out Note 2 MSM548263 t RP STOP Data Out Data Out t SQD Note 2 "H" or "L" 24/40 ...
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... QSF = "H"-- Upper SAM (256 - 511) is active RAS t CSH t RSH t CAS t RAL t t ASC CAH SAM Start t CSD Open t RSD t SCP Note 2 t SDS Data In t SDD t CQD Note 3 MSM548263 SCC SDH SDS SDH Data In Note 3 "H" or "L" 25/40 ...
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... CSH t RSH t CAS t RAL t t ASC CAH SAM Start Sj t CTH t ATH Open t RTH t SCC t t SCP STOP SDS SDH SDH Data In Data In Note 2 MSM548263 t RP STOP Data In Data In t SQD Note 2 "H" or "L" 26/40 ...
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... SCP SC t SDS SDQ1 - 8 Data In Data In t SEP t SCC SCP t t SEA Data t SEP SWH SWIS SWIH t SDH MSM548263 t t SCA SCA t SOH SOH Data Out Data Out t SWS t SDS t t SZE SDH Data In Data In "H" or "L" 27/40 ...
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... PIN FUNCTIONS Address Input The 18 address bits decode 8 bits of the 2,097,152 locations in the MSM548263 memory array. The address bits are multiplexed to 9 address input pins (A0 - A8) as standard DRAM. 9 row address bits are latched at the falling edge of RAS. The following 9 column address bits are latched at the falling edge of CAS ...
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... Serial Input/Output: SDQ1 - SDQ8 Serial input/output mode is determined by the most recent read or write transfer cycle. When a read transfer cycle is performed, the SAM port is in the output mode. When a write or pseudo write transfer cycle is performed, the SAM port is switched from output mode to input mode. MSM548263 29/40 ...
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... OPERATION MODES Table-1 shows the function truth table for a listing of all available RAM ports and transter operation of MSM548263. The RAM port and data transfer operations are determined by the state of CAS, TRG, WE and DSF at the falling edge of RAS, and by the level of DSF at the falling edge of CAS. ...
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... RAM PORT OPERATION Extended RAM Read Cycle: RAS falling edge --- TRG = CAS = "H", DSF = "L" The MSM548263 offers an accelerated page mode cycle (EXTENDED PAGE MODE) by eliminating output disable from CAS "high", and it allows CAS precharge time (t output data becoming invalid. This new data out operates (Extended data out) as any RAM read or Page Mode Read, except data will be held valid after CAS goes " ...
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... Semiconductor Load/Read Color Register: RAS falling edge --- CAS = TRG = WE = DSF = "H" The MSM548263 is provided with an on-chip 8-bit color register for use during the flash write or block write operation. Each bit of the color register corresponds to one of the DRAM I/O blocks. The data presented on the DQi lines is subsequently latched into the color register at the falling edge of either CAS or WE whichever occurs later. The read color register cycle is activated by holding WE " ...
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... SAM pointer moves to the TAP location selected for the second split SAM to shift data in or out sequentially, starts from this TAP location at the most significant bit (511 or 255), and finally wraps around to the least significant bit. TAP TAP 255 256 257 MSM548263 511 33/40 ...
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... The conventional transfer and split transfer modes are controlled by the DSF input signal. Data transfer are invoked by holding the TRG signal "low" at the falling edge of RAS. The MSM548263 supports 4 types of transfer operations: Read transfer, Split read transfer, Write transfer and Split write transfer as shown in the truth table. The type of transfer operation is determined by the state of CAS, WE and DSF latched at the falling edge of RAS ...
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... AX8). SCA during the RAS cycle. A rising edge of the from the falling edge of the CAS, at which time CSD MSM548263 from the rising edge of after the SC high time TSD , t , and t /t RTH CTH TSL TSD ...
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... Semiconductor Split Data Transfer and QSF The MSM548263 features a bidirectional split data transfer capability between the RAM and SAM. During split data transfer operation, the serial register is split into two halves which can be controlled independently. Split read or split write transfer operation can be performed to or from one half of the serial register, while serial data can be shifted into or out of the other half of the serial register ...
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... Programmable SAM Stops in Split Transfer Cycle The MSM548263 has a boundary split register operation using programmable stops CBRS cycle has been performed, the split transfer cycle performs the boundary operation. Figure 2 shows an example of a boundary split register (4 stop points). The stop points define a SAM location at which the access will change from one half of the SAM to the other half (at the TAP address) ...
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... Therefore recommended that the initial state be set (ex. Perform a CBRR cycle to select Non Persistent Write-per-bit mode) after the initialization of the device is performed and before valid operations begin. SAM Stop Boundary Table Address MSM548263 Size of Partition 256 128 38/40 ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM548263 (Unit : mm) Package material Epoxy resin ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM548263 (Unit : mm) Package material Epoxy resin ...