SAB-C505L-4EM Infineon Technologies AG, SAB-C505L-4EM Datasheet
SAB-C505L-4EM
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SAB-C505L-4EM Summary of contents
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Microcomputer Components 8-bit CMOS Microcontroller C505L Data Sheet 06. ...
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... For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com. Enhanced Hooks Technology Siemens. Edition 06.99 Published by Infineon Technologies AG i. Gr., St.-Martin-Strasse 53 D-81541 München © Infineon Technologies AG 1999 All Rights Reserved. ...
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CMOS Microcontroller Advance Information Features • Fully compatible with the standard 8051 microcontroller • Superset of the 8051 architecture with 8 datapointers • MHz operating frequency – 375 ns instruction cycle time @ 16 MHz – ...
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... Software power-down mode with wake up capability through INT0 pin or Real-Time Clock • P-MQFP-80 package • Temperature ranges: SAB-C505L T SAF-C505L T SAK-C505L T Ordering Information The ordering code for Infineon Technologies’ microcontrollers provides an exact reference to the required product. This ordering code identifies: • ...
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V AREF V AGND XTAL1 XTAL2 RESET EA ALE PSEN XTAL3 XTAL4 C31 Figure 2 Logic Symbol Data Sheet Port 8-Bit Digital Port 8-Bit Digital 8-Bit ...
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P0.7 / AD7 61 P0.6 / AD6 62 P0.5 / AD5 63 P0.4 / AD4 64 P0.3 / AD3 65 P0.2 / AD2 66 P0.1 / AD1 67 P0.0 / AD0 P1.0 / ...
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Table 1 Pin Definitions and Functions Symbol Pin Number R0-R3 1 C0-C15 5- Input O = Output ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P4.0-P4.7 21- P5.0-P5.5 29- Input O = Output Data Sheet I/O*) Function I/O ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P3.7-P3.0 35- Input O = Output Data Sheet I/O*) Function I/O Port 8-bit quasi-bidirectional port with ...
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... It is activated every three oscillator periods except during an external data memory access. When instructions are executed from internal program memory (EA = 1), the ALE generation can be disabled by bit EALE in SFR SYSCON. This pin should not be driven during reset operation. I External Access Enable This pin must be held at high level ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number XTAL2 47 XTAL1 48 XTAL4 51 XTAL3 Input O = Output Data Sheet I/O*) Function O XTAL2 Output of the inverting oscillator amplifier. I XTAL1 Input ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P2.7-P2.0 53-60 P0.7-P0.0 61- Input O = Output Data Sheet I/O*) Function I/O Port 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P1.0-P1.7 71- Input O = Output Data Sheet I/O*) Function I/O Port 8-bit quasi-bidirectional port with ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number V 79 AREF V 80 AGND Input O = Output Data Sheet I/O*) Function – Reference voltage for the ...
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V C505L DD V Oscillator SS Watchdog XTAL1 OSC & Timing XTAL2 CPU RESET 8 Datapointers ALE Programmable PSEN Watchdog Timer EA Timer 0 Timer 1 Timer 2 USART Baudrate Generator Real-Time XTAL3 Clock XTAL4 Interrupt Unit ...
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CPU The C505L is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting ...
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Memory Organization The C505L CPU manipulates operands in the following five address spaces: – Kbytes of program memory (32K on-chip OTP memory) – Kbytes of external data memory – 256 bytes of internal data ...
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Reset and System Clock The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (12 oscillator periods) while the oscillator ...
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Figure 7 and Figure 8 show the recommended oscillator circiutries for crystal and external clock operations, respectively, for the system or main clock. *) Crystal or ceramic resonator Figure 7 Recommended Oscillator Circuitries (for XTAL1-XTAL2) External Clock Signal Figure 8 ...
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Multiple Datapointers As a functional enhancement to the standard 8051 architecture, the C505L contains eight 16-bit datapointers instead of only one datapointer. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointer ...
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Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of ...
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... All SFRs with addresses where address bits 0-2 are 0 (e.g. 80 bit-addressable. The 51 SFRs in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C505L are listed in Table 2 and Table 3 ...
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... Port 4 P5 Port 5 1) Bit-addressable SFRs 2) This SFR is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X” means that the value is undefined and the location is reserved 4) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set. ...
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... Power Control Register 1 4) Modes 1) Bit-addressable SFRs 2) This SFR is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X” means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. ...
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... Real-Time Clock Interrupt Register 3 RTINT4 Real-Time Clock Interrupt Register 4 1) Bit-addressable SFRs 2) This SFR is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X” means that the value is undefined and the location is reserved. 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. ...
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... OWDS WDTS . SRELL means that the value is undefined and the location is reserved 2) Bit-addressable SFRs 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Data Sheet Bit 6 Bit 5 Bit 4 Bit ...
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... ADCON0 00X0 0000 B D9 ADDATH ADDATL 00XX XXXX means that the value is undefined and the location is reserved 2) Bit-addressable SFRs Data Sheet Bit 6 Bit 5 Bit 4 Bit INT1 – EALE RMAP – EX5 EX4 – – ...
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... means that the value is undefined and the location is reserved. 2) Bit-addressable SFRs. 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These are read-only registers. 5) The content of this SFR varies with the actual of the step C505L (e.g. 01 ...
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Table 4 Contents of the LCD and the RTC Registers in Numeric Order of Their Addresses Addr. Register Content after Reset F3DC DAC0 F3DD LCON F3DE LCRL F3DF LCRH 00 H ...
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... C). The 8 analog inputs, AN0-AN7, are located at the port 1 pins P1.0 to P1.7. After reset, all analog inputs are disabled and the related pins of port 1 are configured as digital inputs. The analog function of the specific port 1 pins are enabled by bits in the SFRs P1ANA. Writing bit position of P1ANA assigns the corresponding pin to operate as analog input ...
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Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 6: Table 6 Timer/Counter 0 and 1 Operating Modes Mode Description 0 8-bit timer/counter with a divide-by-32 prescaler 1 ...
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Timer/Counter 2 with Compare/Capture/Reload The timer 2 of the C505L provides additional compare/capture/reload features, which allow the selection of the following operating modes: – Compare : PWM signals with 16-bit/300 ns resolution (@ 20 MHz clock) – ...
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Timer 2 Operating Modes The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer overflow flag ...
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Timer 2 Compare Modes The compare function of a timer/register combination operates as follows: the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer ...
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Compare Mode 1 If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, it can ...
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Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in Table 7. Table 7 USART Operating Modes SCON Description Mode SM0 SM1 Shift ...
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Timer 1 Overflow Baud Rate Generator f OSC (SRELH SRELL) ÷ 6 Note: The switch configuration shows the reset state. Figure 15 Block Diagram of Baud Rate Generation for the Serial Interface Table 8 below lists the values/formulas for the ...
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LCD Controller Unit The Liquid Crystal Display (LCD) controller unit in the C505L is designed for the control of an LCD display module of 128 display segments (4 rows and 32 columns) using the 1/4 duty-cycle driving method. The C505L ...
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LCDIN f RTC f OSC 0 CSEL Figure 17 LCD Clocking The generated LCD clock has a duty-cycle of 50%. The table in Figure 17 shows the recommended reload values at different input frequencies ( 360 Hz. ...
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Display Voltage Levels The LCD controller outputs three voltage levels required for driving the LCD display module. These voltage levels are generated by a programmable 8-bit D/A converter via the register DAC0 and a resistive divider network. The D/A converter ...
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Real-Time Clock The real-time clock unit of the C505L contains a dedicated oscillator and a 47-bit timer which is used to count time elapsed with respect to an initial time. The C505L real-time clock does not provide for any error ...
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Real-Time Clock in Power Saving Modes Once started in the normal mode, the oscillator as well as the whole real-time clock could remain in operation during certain power-down modes where the power supply could be reduced to a minimum of ...
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A/D Converter The C505L includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity ...
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IEN1 ( EXEN2 EXEN2 SWDT SWDT IRCON ( EXF2 TF2 P1ANA ( EAN7 EAN6 ADCON1 ( ADCL1 ADCL2 ADCON0 ( CLK Port 1 MUX Clock f OSC Prescaler 32, ...
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Interrupt System The C505L provides 12 interrupt vectors with four priority levels. Five interrupt requests can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter) and six interrupts may be triggered externally (P3.2/INT0, ...
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... P3.2 / INT0 IT0 TCON Converter Timer 0 Overflow Software Interrupt Bit addressable Request flag is cleared by hardware Figure 21 Interrupt Structure, Overview Part 1 Data Sheet IE0 0003 H EX0 TCON.1 IEN0.0 IADC 0043 H IRCON.0 EADC IEN1.0 IP1.0 TF0 000B H TCON.5 ET0 IEN0.1 SWI 004B H IRCON.1 ESWI IEN1 ...
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... P3.3 / INT1 IT1 TCON.2 P1.0 / AN0 / INT3 / CC0 I3FR T2CON.6 Timer 1 Overflow P1.1 / AN1 / INT4 / CC1 Bit addressable Request flag is cleared by hardware Figure 22 Interrupt Structure, Overview Part 2 Data Sheet IE1 0013 H TCON.3 EX1 IEN0.2 IEX3 0053 H IRCON.2 EX3 IEN1.2 IP1.2 TF1 001B H TCON.7 ET1 IEN0 ...
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... USART TI SCON.1 P1.2 / AN2 / INT5 / CC2 Timer 2 TF2 Overflow IRCON.6 P1.5 / AN5 / EXF2 T2EX IRCON.7 EXEN2 IEN1.7 P1.3 / INT6 / CC3 Bit addressable Request flag is cleared by hardware Figure 23 Interrupt Structure, Overview Part 3 Data Sheet >1 0023 H ES IEN0.4 IEX5 0063 H IRCON.4 EX5 IEN1.4 IP1.4 >1 002B H ET2 IEN0 ...
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Fail Save Mechanisms The C505L offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure: – a programmable watchdog timer (WDT), with variable time-out period from 192 approx. 393 ...
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Oscillator Watchdog The oscillator watchdog unit serves for four functions: – Monitoring of the on-chip oscillator’s function The watchdog supervises the on-chip oscillator’s frequency lower than the frequency of the auxiliary RC oscillator in the watchdog unit, ...
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EWPD WS IRTC (RTCON.2) Control P3.2 / INT0 Logic Start / Stop RC f Oscillator RC 3 MHz Start / XTAL2 Stop On-Chip XTAL1 Oscillator Figure 25 Block Diagram of the Oscillator Watchdog Data Sheet Power - Down (PCON1.0) Mode ...
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Power Saving Modes The C505L provides three basic power saving modes, the idle mode, the slow-down mode and the software power down mode. – Idle mode The CPU is gated off from the oscillator. All peripherals are still provided with ...
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Table 10 Power Saving Modes Overview Mode Entering Sequence Example Idle mode ORL PCON, #01H ORL PCON, #20H Slow Down Mode In normal mode: ORL PCON, #10H With idle mode: ORL PCON, #01H ORL PCON, #30H Software ... Power Down ...
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OTP Memory Operation The C505L contains a 32 Kbyte one-time programmable (OTP) program memory. With the C505L fast programming cycles are achieved (1 byte in 100 s). Also several levels of OTP memory protection can be selected. For programming of ...
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Pin Configuration in Programming Mode N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N. Figure 27 P-MQFP-80 Pin Configuration of the ...
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Table functional description of all C505L pins that are required for OTP memory programming. Table 11 Pin Definitions and Functions of the C505L in Programming Mode Symbol Pin Number I/O *) Function P-MQFP-80 RESET 43 I PMSEL0 ...
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Table 11 Pin Definitions and Functions of the C505L in Programming Mode (cont’d) Symbol Pin Number I/O *) Function P-MQFP-80 V 49, 70 – 50, 69 – DD A0-A7, 60-53 I A8-A14 (Port 2) PSEN 44 I PROG ...
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Basic Programming Mode Selection The basic programming mode selection scheme is shown in Figure 28 Clock (XTAL1 / XTAL2) RESET PSEN PMSEL1,0 PROG PRD PSEL PALE During this period signals are not actively driven ...
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... Protection Type The OTP lock feature is disabled. During normal operation of the C505L, the state of the EA pin is not latched on reset. During normal operation of the C505L, MOVC instructions executed from external program memory are prevented from fetching code bytes from internal memory sampled and latched on reset ...
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Version Bytes The steppings of the C505L versions will contain the following version register/byte information: Stepping Version Byte 0 = VR0 (mapped addr. FC C505L CA-Step C5 H Note: Future steppings of C505L would have a different version byte 2 ...
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Absolute Maximum Ratings Parameter Storage temperature Voltage on V pins with respect ground ( ) SS Voltage on any pin with respect V to ground ( ) SS Input current on any pin during overload condition Absolute ...
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... Operating Conditions Parameter Supply Voltage (Normal mode) Supply Voltage (Software Power down mode 3 only) Ground voltage Ambient temperature SAB-C505L SAF-C505L SAK-C505L Analog reference voltage Analog ground voltage Analog input voltage CPU clock Data Sheet Symbol Limit Values min. max. V 5.5 4. ...
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DC Characteristics (Operating Conditions apply) Parameter Input low voltages all except EA, RESET, XTAL3 EA pin RESET pin XTAL3 Input high voltages except XTAL1, RESET, XTAL3 and EA XTAL1 RESET, EA XTAL3 Output low voltages Ports ...
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Power Supply Current (Operating Conditions apply) Parameter Active Mode 16 MHz 20 MHz Idle Mode 16 MHz 20 MHz Active Mode with 16 MHz slow-down enabled 20 MHz Idle Mode with 16 MHz slow-down enabled 20 MHz Power down current: ...
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... XTAL1 driven with t V RESET = all other pins are disconnected; the microcontroller is put into slow-down mode by SS software (idle mode with slow-down) is measured with all output pins disconnected and with all peripherals disabled; DD XTAL1 driven with ns, 50% duty cycle ...
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Figure 29 I Diagram DD Table 14 Power Supply Current Calculation Formulas Parameter Active mode Idle mode Active mode with slow-down enabled Idle mode with slow-down enabled Note ...
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LCD-Output Characteristics (Operating Conditions apply) Parameter Full range output voltage, of D/A Converter Settling Time of D/A Converter Output DC differential non-linearity of D/A Converter DC integral non-linearity of D/A Converter DC Offset Voltage of D/A Converter LCD Voltage levels ...
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A/D Converter Characteristics (Operating Conditions apply) Parameter Symbol V Analog input voltage AIN t Sample time S t Conversion cycle time ADCC Total unadjusted error Internal resistance of AREF reference voltage source R Internal resistance of ASRC ...
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Notes may exceed AIN AGND AREF cases will be X000 or X3FF During the sample time the input capacitance internal resistance of the analog source must allow the capacitance to reach their ...
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AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle) (Operating Conditions apply for port 0, ALE and PSEN outputs = 100 pF; L Program Memory Characteristics Parameter ALE pulse width Address setup to ALE Address hold after ALE ...
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AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle) (cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to ...
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AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle) (cont’d) External Clock Drive Characteristics Parameter Symbol Oscillator period CLP High time TCL Low time TCL Rise time Fall time F Oscillator duty cycle DC Clock cycle TCL ...
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AC Characteristics (20 MHz, 0.5 Duty Cycle) (Operating Conditions apply) C for port 0, ALE and PSEN outputs = 100 pF; L Program Memory Characteristics Parameter ALE pulse width Address setup to ALE Address hold after ALE ALE to valid ...
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AC Characteristics (20 MHz, 0.5 Duty Cycle) (cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data ...
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ALE PSEN Port 0 Port 2 Figure 30 Program Memory Read Cycle Data Sheet t LHLL t t AVLL PLPH t LLPL t LLIV t PLIV t AZPL t LLAX Instr.IN t AVIV A8 - A15 73 ...
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ALE PSEN RD t AVLL from Port DPL t AVWL Port 2 Figure 31 Data Memory Read Cycle Data Sheet t LLDV t t LLWL RLRH t RLDV LLAX2 t RLAZ Data IN ...
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ALE PSEN WR t AVLL from Port DPL t AVWL Port 2 Figure 32 Data Memory Write Cycle TCL XTAL1 Figure 33 External Clock Drive on XTAL1 Data Sheet t t LLWL WLWH ...
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AC Characteristics of Programming Mode 11 Parameter PALE pulse width PMSEL setup to PALE rising edge Address setup to PALE, PROG, or PRD falling edge Address hold ...
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PAW PALE t PMS PMSEL1,0 t PAS Port 2 A8-A14 Port 0 PROG Notes: PRD must be high during a programming write cycle. Figure 34 Programming Code Byte - Write Cycle Timing Data Sheet PAH A0-A7 ...
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PAW PALE t PMS PMSEL1,0 t Port 2 A8-A14 Port 0 PRD Notes: PROG must be high during a programming read cycle. Figure 35 Verify Code Byte - Read Cycle Timing Data Sheet PAS PAH t ...
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PMSEL1,0 Port 0 t PMS PROG PRD Note: PALE should be low during a lock bit read / write cycle. Figure 36 Lock Bit Access Timing PMSEL1,0 Port 2 Port 0 PRD Note: Figure 37 Version Byte Read Timing Data ...
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OTP Verification Mode Characteristics Note: ALE pin described below is the pin 45. Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency ALE Port 0 P3.5 Figure 38 ...
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Inputs during testing are driven at Timing measurements are made at Figure 39 AC Testing: Input, Output Waveforms V +0.1 V Load V Load -0 Load For timing purposes a port ...
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Crystal Oscillator Mode C 4 32.768 MHz C 3 Crystal Mode : pF; 3 Figure 42 Recommended Oscillator Circuits for Real-Time Clock Oscillator at XTAL3 The recommended oscillator circuitry for the Real-Time Clock oscillator configuration using a ...
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Plastic Package, P-MQFP-80-1 (SMD) (Plastic Metric Quad Flat Pack) 0.65 0.3 ±0. Index Marking 1) Does not include plastic or metal protrusions of 0.25 max per side Figure 43 P-MQFP-80-1 Package Outline Sorts of Packing Package outlines ...