AL102 Allayer Communications, AL102 Datasheet
AL102
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AL102 Summary of contents
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... Secure mode traffic filtering Product Description The AL102A is an eight-port 10/100 Mbit/s dual speed Ethernet switch. A low-cost Fast Ethernet switch can be implemented using the AL102A with low-cost SGRAM. The AL102A also supports VLAN and multiple port aggregation trunks. 10/100 MAC ...
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... Life Support Applications Allayer Communications products are not designed for use in life support appliances, systems, or devices where malfunctions can be reasonably expected to result in personal injury. 5/00 Reference Only / Allayer Communications ...
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... AL102A Overview................................................................................................... 5 2. Pin Descriptions....................................................................................................... 7 3. Functional Description........................................................................................... 16 3.1 Data Reception............................................................................................... 16 3.1.1 Illegal Frame Length .............................................................................. 16 3.1.2 Long Frames .......................................................................................... 16 3.1.3 False Carrier Events ............................................................................... 16 3.1.4 Frame Filtering....................................................................................... 16 3.2 Frame Forwarding.......................................................................................... 17 3.2.1 Broadcast Storm Control........................................................................ 17 3.2.2 Frame Transmission ............................................................................... 18 3.2.3 Frame Generation................................................................................... 18 3.3 Half Duplex Mode Operation ........................................................................ 18 3.4 Secure Mode Operation ................................................................................. 18 3.5 Address Learning ........................................................................................... 19 3.5.1 Address Aging........................................................................................ 19 3.6 VLAN Support............................................................................................... 19 3 ...
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... EEPROM Map ....................................................................................... 31 3.15 SGRAM Interface .......................................................................................... 35 4. Register Descriptions............................................................................................. 36 5. Timing Requirements............................................................................................. 49 6. Electrical Specifications ........................................................................................ 57 7. AL102A Mechanical Data ..................................................................................... 58 8. Appendix I (VLAN Mapping Work Sheet) ........................................................... 59 9. Appendix II (Port to Trunk Port Assignment Work Sheet) ................................... 60 10. Appendix III (Suggested Memory Components)................................................... 61 5/00 Reference Only / Allayer Communications 4 ...
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... The device also provides two levels of security for intrusion protection. Security can be implemented on a per port basis. The AL102A operates only in the store and forward mode. The entire frame is checked for error. Frames with errors are automatically filtered and will not be forwarded to the destination port. ...
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... M2TXD3 50 M2TXD2 M2TXD1 Vcc M2TXD0 M2TXEN 55 M2TXCLK M2RXER M2RXCLK M2RXDV M2RXD0 60 M2RXD1 Figure 2 AL102A Pin Diagram (Top View) 5/00 Reference Only / Allayer Communications NC NC 190 Vcc GND M7RXD3 GND M7RXD2 185 M7RXD1 M7RXD0 M7RXDV M7RXCLK M7RXER M7TXCLK 180 M7TXEN M7TXD0 ...
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... Transmit Clock Input. 25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s. I Receive Data - NRZ from the transceiver. For MII interface, signal RX_DV, RX_ER and RX_D0 through RX_D3 are sampled by the rising edge of RX_CLK. I Receive Data Valid. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 7 ...
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... Transmit Clock Input. 25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s. I Receive Data - NRZ from the transceiver. For MII interface, signal RX_DV, RX_ER and RX_D0 through RX_D3 are sampled by the rising edge of RX_CLK. I Receive Data Valid. I Receive Clock. I Receive Data Error. I Carrier Sense. I Collision Detect. Reference Only / Allayer Communications DESCRIPTION 8 ...
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... Transmit Clock Input. 25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s. I Receive Data - NRZ from the transceiver. For MII interface, signal RX_DV, RX_ER and RX_D0 through RX_D3 are sampled by the rising edge of RX_CLK. I Receive Data Valid. I Receive Clock. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 9 ...
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... Transmit Clock Input. 25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s. I Receive Data - NRZ from the transceiver. For MII interface, signal RX_DV, RX_ER and RX_D0 through RX_D3 are sampled by the rising edge of RX_CLK. I Receive Data Valid. I Receive Clock. I Receive Data Error. I Carrier Sense. I Collision Detect. Reference Only / Allayer Communications DESCRIPTION 10 ...
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... Transmit Clock Input. 25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s. Receive Data - NRZ data from the transceiver. For MII I interface, signal RX_DV, RX_ER and RX_D0 through RX_D3 are sampled by the rising edge of RX_CLK. Receive Data Valid. I Receive Clock. I Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 11 ...
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... Table 10: MII PHY Management Interface I/O O PHY Management Clock. I/O PHY Management Data Input and Output. Table 11: Power Interface PIN NUMBER 217, 232, 248 134 Reference Only / Allayer Communications DESCRIPTION DESCRIPTION DESCRIPTION Ground 3.3V Supply Voltage. Supply Voltage for MII Interface. VccM = 5V (5V MII interface) VccM = 3.3V (3.3V MII interface) 12 ...
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... Mbit/s SGRAM this pin is PBA 9. O SGRAM Address. For 16 Mbit/s SGRAM, this pin is PBA9 and for 8 Mbit/s SGRAM this pin is PBA 8. O SGRAM Address. For 16 Mbit/s SGRAM, this pin is PBA8 and unconnected when connected to 8 Mbit/s SGRAM. Reference Only / Allayer Communications DESCRIPTION 13 ...
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... Reference Only / Allayer Communications DESCRIPTION Device ID Number. For the AL102A, both pins should be connected to ground. Reset Test Mode Pin. This pin should be grounded for normal operation. This pin bypasses the EEPROM setup. This pin should be tied to ground ...
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... AL102A Interface Block Diagram 10/100 MAC MXTXD3 MXTXD2 MXTXD1 10/100 MAC MXTXD0 10/100 MAC MXTXEN MXTXCLK MXRXD3 10/100 MAC MXRXD2 MXRXD1 10/100 MAC MXRXD0 MXRXDV 10/100 MAC MXRXCLK MXRXER 10/100 MAC MXCRS MXCOL 10/100 MAC 32 PBD[n] 9 PBA[n] PBBA Buffer PBCS Manager ...
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... The port will go into the receive-state when RX_DV in the MII interface is asserted. The MII (Media Independent Interface) presents the received data in four-bit nibbles that are synchronous to the receive clock (25 MHz for 100 Mbit/s or 2.5 MHz for 10 Mbit/s). The AL102A will then attempt to detect the occurrence of the SFD (Start Frame Delimiter) pattern “10101011.” All preamble data prior to SFD are discarded ...
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... Broadcast Storm Control One of the unique features provided by the AL102A is Broadcast Storm Control. This option allows the user to limit the number of broadcast frames into the switch. This option can be implemented on a per port basis. A threshold number of broadcast frames can be programmed in System Register II (register 01) ...
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... IEEE back off algorithm. 3.4 Secure Mode Operation The AL102A provides security support on a per port basis. Whenever the secure mode is enabled, the port will stop learning new addresses. The address table of each port will remain unchanged. In this mode of operation, the address lookup table will freeze and no additional new address will be learned ...
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... VLAN Support Each port of the AL102A can be assigned to one or multiple VLANs. Frames from the source port will only be forwarded to destination ports within the same VLAN domain. A broadcast/multicast frame will be forwarded to all ports within the VLAN(s) except the source port itself. A unicast frame will be forwarded to the destination port only if the destination port is in the same VLAN as the source port ...
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... Table 14: VLAN Map for an 8-Port Switch BIT Reference Only / Allayer Communications ...
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... When a frame is received from any one of the trunk ports, it will be routed to the destination port within the VLAN. In essence, the AL102A treats a trunk as any single port within the same VLAN. If the ports traffic is evenly distributed among all the trunk ports, load balancing is achieved and the aggregate bandwidth of the trunk can be as high as 800 Mbit/s (full-duplex) ...
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... Therefore, the port to trunk port register bits are as follows. 08.2= 0, 08.3 =1 09.2= 1. 09.3 =0 10.2= 1, 10.3 =1 11.2= 1. 11.3 =0 12. For the trunk ports, trunk ports should be assigned with their own the port number in the port to trunk port register. The port to trunk port bits. 5/00 AL102A Trunk Port 0 Reference Only / Allayer Communications 4 5 ...
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... Reference Only / Allayer Communications ...
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... Carrier based backpressure is generated by the AL102A, when the switch port’s frame buffer is full. The AL102A will cease to jam the line, when the port has buffer space available for frame reception. The IPG of the jamming signal can be programmed be either 64BT or 96BT. ...
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... AL102A are stored into the shared memory buffer, and are lined up in the transmission queues of corresponding destination port. Each port of the AL102A has an input frame queue, and a dedicated queue to buffer the locally generated management event messages. Each output port maintains an output frame queue for, and a dedicated multicast queue for outgoing multicast frame parking ...
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... The transmit data is clocked out by the rising edge of the transmit clock (TX_CLK). Prior to any transaction, the AL102A will output 32-bits of “1” preamble signal and then after the preamble, a “01” signal is used to indicate the start of the frame. ...
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... After the completion of the write transaction, the line will be put in a high impedance state. For a read operation, the AL102A will output a “10” to indicate read operation after the start of frame indicator. Following the “10” read signal will be the five-bit ID address of the PHY device and the five-bit register address ...
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... Device Type 1 If the reset pin is held low, the AL102A’s EEPROM interface will go into a high impedance state. This feature is very useful for reprogramming the EEPROM during installation or reconfiguration. The EEPROM can be reprogrammed by an external parallel port. For reprogramming using a parallel port, a signal is used to hold the RESET pin low ...
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... Write Cycle Timing The EECLK is an output from the AL102A while EEDIO is a bi-directional signal. When accessing the EEPROM, the reset pin has to be held low or initialization of the AL102A must be finished before a writing operation can begin. A typical write operation is shown in Start ...
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... The customer can now program the AL102A as an EEPROM. The read and write timing is the same as an EEPROM. Because you read as well as write to the AL102A, the registers status can be read from the AL102A. This will serve as a very useful tool for diagnostic of an unmanaged switch. ...
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... Table 16 shows the EEPROM address map cross-referenced to the register/bit set of the AL102A. Addresses 00 through 6D are for configuring the device. They are downloaded by the AL102A after reset or power up. Since the AL102A registers are 16-bit wide, it takes two EEPROM addresses for each AL102A register. Even numbered EEPROM addresses corresponds to the upper byte of the AL102A registers while the odd numbered EEPROM addresses corresponds to the lower byte of the AL102A registers ...
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... Port 1 Configuration I 20-21 Port 1 Configuration II 22-23 Port 2 Configuration I 24-25 Port 2 Configuration II 26-27 Port 3 Configuration I 28-29 Port 3 Configuration II 2A-2B Port 4 Configuration I 2C-2D Port 4 Configuration II 2E-2F Port 5 Configuration I 30-31 Port 5 Configuration II 32-33 Port 6 Configuration I 5/00 Table 17: AL102A EEPROM Mapping DESCRIPTION Reference Only / Allayer Communications AL102A REGISTER/BIT 00.15 to 00.8 00.7 to 00.0 01.15 to 01.0 02.15 to 02.0 03.15 to 03.0 04.15 to 04.0 05.15 to 05.0 06.15 to 06.0 07.15 to 07.0 08.15 to 08.0 09.15 to 09.0 0A.15 to 0A.0 0B.15 to 0B.0 0C.15 to 0C.0 0D.15 to 0D.0 0E.15 to 0E.0 0F.15 to 0F.0 10.15 to 10.0 11 ...
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... Table 17: AL102A EEPROM Mapping (Continued) 34-35 Port 6 Configuration II 36-37 Port 7 Configuration I 38-39 Port 7 Configuration II 3A-3B Port 0 VLAN Map I 3C-3D Port 0 VLAN Map II 3E-3F Port 1 VLAN Map I 40-41 Port 1 VLAN Map II 42-43 Port 2 VLAN Map I 44-45 Port 2 VLAN Map II 46-47 Port 3 VLAN Map I 48-49 Port 3 VLAN Map II 4A-4B Port 4 VLAN Map I 4C-4D Port 4 VLAN Map II ...
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... Table 17: AL102A EEPROM Mapping (Continued) 6F Last Entry Address 70-71 Static Entry 1 (Port Number) 72-73 Static Entry 1 (MAC [47:32]) 74-75 Static Entry 1 (MAC [31:16]) 76-77 Static Entry 1 (MAC [15:0]) 78-7f Static Entry 2 80-87 Static Entry 2 88-8f Static Entry 4 90-97 Static Entry 5 98-9f Static Entry 6 A0-A7 Static Entry 7 A8-AF Static Entry 8 B0-B7 Static Entry 9 B8-BF Static Entry 10 C0-C7 Static Entry 11 ...
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... SGRAM Interface All ports of AL102A work in Store-And-Forward mode so that all ports can support both 10 Mbit/s and 100 Mbit/s data speed. The AL102A utilizes a central memory buffers pool, which is shared by all ports within the same device. After a frame is received passed across the SGRAM interface and stored in the buffer ...
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... Monitored Destination Host I [47:32] Monitored Destination Host II [31:16] Monitored Destination Host III [15:0] Port 0 Configuration I Port 0 Configuration II Port 1 Configuration I Port 1 Configuration II Port 2 Configuration I Port 2 Configuration II Port 3 Configuration I Port 3 Configuration II Port 4 Configuration I Port 4 Configuration II Port 5 Configuration I Port 5 Configuration II Port 6 Configuration I Port 6 Configuration II Reference Only / Allayer Communications 36 ...
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... Port 1 to Trunk Port Assignment Port 2 to Trunk Port Assignment Port 3 to Trunk Port Assignment Port 4 to Trunk Port Assignment Port 5 to Trunk Port Assignment Port 6 to Trunk Port Assignment Port 7 to Trunk Port Assignment Reserved Reserved Reserved Reserved Reference Only / Allayer Communications 37 ...
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... DISABLE state. Switch Table Entry Aging Control. 0: Disable. The table aging process will be stopped. 1: Enable. The table aging process will be running to age every dynamically learned table entries. Table Convergence Control. Set all to zero. Reference Only / Allayer Communications DESCRIPTION 38 ...
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... Disable. Device will perform the IEEE standard exponential back off algorithm when a collision occurs. 1: Enable. When collisions occur, the AL102A will back off slots. Retry on Excessive Collision. 0: Normal collision handling. 1: Retry transmission after 16 consecutive collisions. ...
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... IPG = 64BT. IPG Control. 0: IPG = 96BT. 1: IPG = 64BT. Reserved (Must set to 0). SGRAM Select Mbit SGRAM Mbit SGRAM. Back Pressure Control. 0: Carrier based. 1: Collision based. Reserved (Must set to 0). 0: Flow control multicast. 1: Flow control broadcast. Reference Only / Allayer Communications DESCRIPTION 40 ...
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... PHY’s Data Rate Status Register Bit Number. PHY’s Operating Duplex Mode Status Register Bit Number. Bit should be set at 0. Monitored Port ID. Snooping Port ID for Incoming Frame Flow. Snooping Port ID for Outgoing Frame Flow. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 41 ...
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... If the uplink is a trunk, then the bits should read [100][trunk number]. The trunk number is numbered [Dev_ID][Trunk_ID]. If the local port is an uplink port, the uplink ID should be its own port ID. Any frame with unlearned SA will then be filtered. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION Monitored Destination Host MAC Address ...
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... BPDUs will be masked from the path to the PHY. 11: Forwarding. All incoming frames from the PHY will be learned from their source information; all incoming frames will be forwarded based on the switch routing decision; all outgoing frames will be transmitted to the PHY. Reserved (Must set to 0) Reference Only / Allayer Communications DESCRIPTION 43 ...
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... Link Down. 1: Link Up. 100 Full Duplex Mode. 100 Half Duplex Mode. 10 Full Duplex Mode. 10 Half Duplex Mode. NAME Dev0Map Port VLAN Map corresponding to the port7~port0 of the device with Dev_ID of 00. 0: Non-member port. 1: Member port. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 44 ...
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... Trunk Port of Trunk 0. 00: Port 0, 01: Port 1 10: Port 2, 11: Port 3 NAME Reserved Reserved (Must set to 0) EEPROM Checksum Error. SGRAM Initialization Done. SRAMinit SRAM Initialization Done. REGinit Register Initialization Done. Traffic Counter. Reserved Chip ID 0000: AL102A Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 45 ...
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... Input buffer full experienced. Table Entry Unavailability for MAC Learning. 0: Normal 1: Unavailability experienced. Port Jabber Status. 0: Normal 1: Jabber experienced. Port Late Collision Status. 0: Normal 1: Late collision experienced. Port Transmit Pause Status transmit pause experienced. 1: Transmit pause experienced. Reference Only / Allayer Communications DESCRIPTION 46 ...
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... Indirect Resource Access Command Register (Register 42) The indirect resource access command allows the management (Reverse EEPROM Method) to access other resources other than the AL102A register values. PHY registers, both internal and external MAC address tables, and SGRAM contents can be accessed using this command. ...
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... The address of the entry within the accessed resource. Indirect Resource Access Data 1. Indirect Resource Access Data 2. Indirect Resource Access Data 3. Indirect Resource Access Data 4. Table 37: Check Sum (Register 47) Checksum value of AL102A register contents. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION ...
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... RXEN RXD Figure 10 MII Receive Timing 5/00 Table 38: MII Transmit Timing DESCRIPTION DATA DATA DATA Table 39: MII Receive Timing DESCRIPTION t t rxds rxdh DATA DATA DATA Reference Only / Allayer Communications MIN TYP MAX txev DATA DATA DATA MIN TYP MAX 10 ...
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... MDC period MDIO setup time MDIO hold time. mh MDC MDIO Figure 11 PHY Management Read Timing 5/00 DESCRIPTION Reference Only / Allayer Communications MIN TYP MAX 420 425 430 420 425 430 840 850 860 ...
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... PBCS#, PBRAS#, PBWE# setup time Precharge command period Auto-refresh to auto-refresh period. RC 5/00 DESCRIPTION Table 42: SGRAM Refresh Timing DESCRIPTION Reference Only / Allayer Communications MIN TYP MAX 420 425 430 420 425 430 840 850 860 MIN ...
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... PBCLK CKH CKS CKE Precharge NOP Command BANK t Address RP Don't Care Figure 13 SGRAM Refresh Timing 5/00 t CHI Auto NOP Refresh t RC Reference Only / Allayer Communications t CL Auto NOP Refresh t RC Active BANK ROW 52 ...
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... OH t Active to precharge command RAS period. t Active to read delay. RCD Note: This timing requirement is for a SGRAM running at CAS Latency 2. Typically a -8 speed grade SGRAM needs to be used. 5/00 Table 43: SGRAM Read Timing DESCRIPTION Reference Only / Allayer Communications MIN TYP MAX - - 2 ...
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... RCD t (Bank 0) RAS Figure 14 SGRAM Read Timing 5/00 t CHI NOP NOP NOP Dout Dout m m CAS Latency 256 location within the same row Reference Only / Allayer Communications BURST NOP NOP NOP TERM. Dout Dout Dout Dout m m+1 m+2 m ...
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... Data in setup time Active to precharge command RAS period. t Active to read delay. RCD Note: This timing requirement is for a SGRAM running at CAS Latency 2. Typically a -8 speed grade SGRAM needs to be used. 5/00 Table 44: SGRAM Write Timing DESCRIPTION Reference Only / Allayer Communications MIN TYP MAX 2 ...
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... DS PBD Din m t (Bank 0) RCD t (Bank 0) RAS Figure 15 SGRAM Write Timing 5/ NOP write NOP NOP t DH Din Din Din m+1 m+2 m+3 256 location within the same row Reference Only / Allayer Communications BURST NOP NOP NOP TERM. Din Din m m-1 Don't Care Undefined 56 ...
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... Input current-low (With no pull-up or pull-down) Vih Input high voltage Vil Input low voltage Icc Supply current 5/00 Table 45: Maximum Ratings Table 46: Recommended Operation Conditions Table 47: DC Electrical Characteristics DESCRIPTION Reference Only / Allayer Communications -0. 3.6V -0.3 ~ Vcc + 0.3V -0.3 ~ Vcc + 0.3V -0.6V to 6.0V -0.6 to Vcc5 + 0.3V -0.6 to Vcc5 + 0. - +150 C 3.3V ± 0.3V ...
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... AL102A Mechanical Data 256 PQFP Package 3.23 ± 0.07 0.25 min. Figure 16 AL102A Mechanical Dimensions 5/00 25.2 28.00 ± 0.10 30.6 ± 0.15 Reference Only / Allayer Communications 0.18 ± 0.04 0.40 4.07 max. 0.60 ± 0.10 1.30 ± 0.10 0.25 58 ...
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... Appendix I ( VLAN Mapping Work Sheet PORT BIT 5/ Reference Only / Allayer Communications 59 ...
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... Appendix II ( Port to Trunk Port Assignment Work Sheet TRUNK / PORT 7 TRUNK 1 6 BITS TRUNK 0 2 BITS 5/00 BIT/ VALUE Reference Only / Allayer Communications ) 60 ...
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... Appendix III (Suggested Memory Components) Note: This is only a partial list of memory components that can be used in Allayer devices. The AL102A uses Frame Buffer SGRAM chips that require 32-bit wide SGRAM or SDRAM, that is 75 MHz or faster with CAS latency 2. DEVICE FREQ. AL102A 75 MHz ...
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... Rev. History (Prelim. 1.1 to 1.2) 1. Reformatted and edited document. 2. Added memory information in appendix III. Rev. History (Prelim 1.2 to 1.3) 3. Added new PHY management timing diagrams. 4. Added new RMII and MII timing diagrams. Prelim 1.3 to Rev. 1.0 1. Fully released document. 5/00 Reference Only / Allayer Communications 62 ...
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... A Address Aging 19 Address Learning 19 AL102A Pin Diagram 6 Appendix I (VLAN Mapping Work Sheet) 59 Appendix II (Port to Trunk Port Assignment Work Sheet) 60 Appendix III (Suggested Memory Components Broadcast Storm Control 17 D Data Reception 16 DC Electrical Characteristics 57 E EEPROM Interface 12, 28 EEPROM Map 31 EEPROM Random Read Cycle 30 ...
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... W Write Cycle Timing 29 5/00 Reference Only / Allayer Communications 64 ...