AT32UC3A0256 Atmel Corporation, AT32UC3A0256 Datasheet - Page 292
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AT32UC3A0256
Manufacturer Part Number
AT32UC3A0256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
Specifications of AT32UC3A0256
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0256-ALUT
Manufacturer:
ATMEL
Quantity:
167
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A0128 PDF datasheet #4
- AT32UC3A0128 PDF datasheet #5
- Current page: 292 of 826
- Download datasheet (11Mb)
32058K AVR32-01/12
25.9.13
Name:
Access Type:
Offset:
Reset value:
• RXEN: Receive Enable
0: Receive is disabled.
1: Receive is enabled.
• TXEN: Transmit Enable
0: Transmit is disabled.
1: Transmit is enabled.
• RXSYN: Receive Sync
0: An Rx Sync has not occurred since the last read of the Status Register.
1: An Rx Sync has occurred since the last read of the Status Register.
• TXSYN: Transmit Sync
0: A Tx Sync has not occurred since the last read of the Status Register.
1: A Tx Sync has occurred since the last read of the Status Register.
• CP1: Compare 1
0: A compare 1 has not occurred since the last read of the Status Register.
1: A compare 1 has occurred since the last read of the Status Register.
• CP0: Compare 0
0: A compare 0 has not occurred since the last read of the Status Register.
1: A compare 0 has occurred since the last read of the Status Register.
• RXBUFF: Receive Buffer Full
0: RCR or RNCR have a value other than 0.
1: Both RCR and RNCR have a value of 0.
• ENDRX: End of Reception
0: Data is written on the Receive Counter Register or Receive Next Counter Register.
RXBUFF
31
23
15
–
–
–
7
Status Register
ENDRX
30
22
14
SR
Read-only
0x40
0x000000CC
–
–
–
6
OVRUN
29
21
13
–
–
–
5
RXRDY
28
20
12
–
–
–
4
TXBUFE
RXSYN
27
19
11
–
–
3
TXSYN
ENDTX
26
18
10
–
–
2
TXEMPTY
RXEN
CP1
25
17
–
9
1
AT32UC3A
TXRDY
TXEN
CP0
24
16
–
8
0
292
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