AT32UC3A1128 Atmel Corporation, AT32UC3A1128 Datasheet - Page 81
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AT32UC3A1128
Manufacturer Part Number
AT32UC3A1128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
Specifications of AT32UC3A1128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
69
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A1128-U
Manufacturer:
ATMEL
Quantity:
13
8.11
32002F–03/2010
Multiple data memory access instructions
These instructions perform multiple data accesses. The incremental accesses are performed as
word accesses. The number of cycles is dependent on the number of registers to load or store,
n. The issue latency must be modified as follows:
The instructions in this group will be aborted immediately if any interrupts are pending, in order
to limit the interrupt latency.
Table 8-8.
Mnemonics
ldm
ldm
ldmts
ldmts
popm
pushm
stm
stm
stmts
stmts
• LDM and POPM will use an additional cycle if testing of R12 is performed
• LDM and POPM that updates PC will cause a change-of-flow, which is performed in parallel
• The issue latency for HSB accesses increases if the HSB bus is busy or the slave inserts wait
with the pointer writeback and therefore has a penalty of only one cycle.
states.
Multiple data memory accesses
E
E
E
E
C
C
E
E
E
E
Operands
Rp, Reglist16
Rp++, Reglist16
Rp, Reglist16
Rp++, Reglist16
Reglist8
Reglist8
Rp, Reglist16
--Rp, Reglist16
Rp, Reglist16
--Rp, Reglist16
Description
Load multiple registers. R12 is
tested if PC is loaded. If PC is in the
register list, p=1, otherwise p=0.
Load multiple registers. R12 is
tested if PC is loaded.
Load multiple registers for task
switch.
Load multiple registers for task
switch.
Pop multiple registers from stack.
R12 is tested if PC is popped.
Store multiple registers.
Store multiple registers.
Store multiple registers for task
switch.
Store multiple registers for task
switch.
Push multiple registers to stack.
Issue
latency
IRAM
1+n+p
2+n
1+n
2+n
2+n
2+n
1+n
2+n
1+n
2+n
AVR32
Issue
latency
HSB
1+2n+p
1+2n
1+2n
1+2n
1+2n
3+n
2+n
3+n
2+n
3+n
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