AT32UC3A1512AU Atmel Corporation, AT32UC3A1512AU Datasheet - Page 527

• Manufacturer Part Number: AT32UC3A1512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
Figure 30-27. Example of an OUT Pipe with 1 Data Bank
Figure 30-28. Example of an OUT Pipe with 2 Data Banks and no Bank Switching Delay
Figure 30-29. Example of an OUT Pipe with 2 Data Banks and a Bank Switching Delay
30.7.3.12
TXOUTI
FIFOCON
TXOUTI
FIFOCON
TXOUTI
FIFOCON
CRC Error
SW
SW
write data to CPU
SW
This error exists only for isochronous IN pipes. It raises the CRC Error interrupt (CRCERRI),
what triggers a PXINT interrupt if CRCERRE = 1.
A CRC error can occur during IN stage if the USB controller detects a corrupted received packet.
The IN packet is stored in the bank as if no CRC error had occurred (RXINI is raised).
write data to CPU
write data to CPU
BANK 0
BANK 0
BANK 0
SW
SW
SW
OUT
OUT
OUT
SW
SW
write data to CPU
(bank 0)
write data to CPU
DATA
BANK 1
(bank 0)
DATA
(bank 0)
BANK 1
DATA
ACK
HW
SW
HW
ACK
HW
ACK
SW
OUT
SW
SW
OUT
write data to CPU
SW
write data to CPU
(bank 1)
write data to CPU
DATA
BANK0
BANK 0
BANK0
(bank 1)
DATA
ACK
AT32UC3A
SW
OUT
ACK
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