AT32UC3A1512AU Atmel Corporation, AT32UC3A1512AU Datasheet - Page 204
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AT32UC3A1512AU
Manufacturer Part Number
AT32UC3A1512AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A1512AU
Flash (kbytes)
512 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
69
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A0128 PDF datasheet #4
- AT32UC3A0128 PDF datasheet #5
- AT32UC3A0128AU PDF datasheet #6
- Current page: 204 of 377
- Download datasheet (5Mb)
204
AVR32
LSL – Logical Shift Left
Architecture revision:
Architecture revision1 and higher.
Description
Shifts all bits in a register the amount of bits specified to the left. The shift amount can reside in
a register or be specified as an immediate. Zeros are shifted into the LSBs. The last bit that is
shifted out is placed in C.
Operation:
I.
II.
III.
Syntax:
I.
II.
III.
Operands:
I.
II.
III.
Status Flags:
Opcode:
Rd ← LSL(Rx, Ry[4:0]);
Rd ← LSL(Rd, sa5);
Rd ← LSL(Rs, sa5);
lsl
lsl
lsl
{d, x, y} ∈ {0, 1, …, 15}
d ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}
{d,s} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}
Format I: Shamt = Ry[4:0], Op = Rx
Format II: Shamt = sa5, Op = Rd
Format III: Shamt = sa5, Op = Rs
Q:
V:
N:
Z:
C:
Rd, Rx, Ry
Rd, sa
Rd, Rs, sa
Not affected
Not affected
N ← RES[31]
Z ← (RES[31:0] == 0)
if Shamt != 0
else
C ← Op[32-Shamt]
C ← 0
32000D–04/2011
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