AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 103
AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
9.2.14.6
32002F–03/2010
Debug Communication Control Register (DCCR)
Table 9-9.
To enable the DCCPU read and DCEMU dirty interrupts the corresponding enable bits must be
set in this register.
Table 9-10.
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
Bit Number
1
1
0
Bit Number
31:2
1
0
Debug Communication Status Register
Debug Communication Control Register
Field Name
CPURI
EMUD
CPUD
Field Name
Reserved
DCCPUIMASK
DCEMUIMASK
Init. Val.
0
0
0
Init. Val.
0x0000_
0000
0
0
Description
CPU Data Read Interrupt flag
0 = DCCPU has not been read since the clearing
of this bit.
1 = DCEMU has been read.
This bit is cleared by writing this bit to 0.
Emulator Data Dirty
0 = DCEMU has not been written to since last read
from CPU.
1 = DCEMU contains a new data value.
This bit is cleared by reading DCEMU.
CPU Data Dirty
0 = DCCPU has not been written to since last read
from emulator.
1 = DCCPU contains a new data value.
This bit is cleared by reading DCCPU.
Description
Reserved
These bits are reserved, and will always read
as 0
DCCPU Interrupt Mask
0 = DCCPU interrupts are disabled.
1 = DCCPU interrupts are enabled.
DCEMU Interrupt Mask
0 = DCEMU interrupts are disabled.
1 = DCEMU interrupts are enabled.
AVR32
103