AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 110
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AT32UC3A4128S
Manufacturer Part Number
AT32UC3A4128S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128S
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A4128S-C1UR
Manufacturer:
ATMEL
Quantity:
2 620
Company:
Part Number:
AT32UC3A4128S-CIUT
Manufacturer:
ATMEL
Quantity:
350
Part Number:
AT32UC3A4128S-CIUT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3A4128S-U
Manufacturer:
ATMEL
Quantity:
12 914
Company:
Part Number:
AT32UC3A4128SC101
Manufacturer:
STM
Quantity:
6 278
Company:
Part Number:
AT32UC3A4128SC1UT
Manufacturer:
ATMEL
Quantity:
6 055
32002F–03/2010
To be able to use JTAG-based debug tools for AVR32 without adapters, it is recommended that
a circuit design using an AVR32 device should use a standard 10-pin 50-mil IDC connector with
the pinout shown in Table 9-16. The signals are described in Table 9-17.
Table 9-16.
Table 9-17.
Signal
TCK
TDO
TMS
N/C
TDI
Pin
TRST_N
TCK
TMS
TDI
TDO
RESET_N
VREF
AVR32 standard JTAG connector pinout. All directions relative to processor
JTAG signals
Direction
Input
Input
Input
Input
Output
Input
Output
Dir
In
Out
In
In
Description
Test Clock. Data is driven on falling edge, sampled on rising edge.
Test Data In
Test Data Out
Device reset
Reference voltage from target. Signals should be driven relative to this
voltage level.
Asynchronous reset for the TAP controller and JTAG registers
Test Mode Select
Pin
1
3
5
7
9
Pin
2
4
6
8
10
Dir
Out
In
Signal
GND
VREF
RESET_N
N/C
N/C
AVR32
110