AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 21
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AT32UC3A4128S
Manufacturer Part Number
AT32UC3A4128S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128S
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 21 of 377
- Download datasheet (5Mb)
2.11.1
32000D–04/2011
SS_STATUS - Secure State Status Register
SS_ADRF, SS_ADRR, SS_ADR0, SS_ADR1 - Secure State Address Registers
SS_SP_SYS, SS_SP_APP - Secure State SP_SYS and SP_APP Registers
SS_RAR, SS_RSR - Secure State Return Address and Return Status Registers
Configuration Registers
Register that can be used to pass status or other information from the secure state to the nonse-
cure state. Refer to
Registers used to partition memories into a secure and a nonsecure section. Refer to
“Secure state” on page 31
Read-only registers containing the SP_SYS and SP_APP values. Refer to
state” on page 31
Contains the address and status register of the sscall instruction that called secure state. Also
used when returning to nonsecure state with the retss instruction. Refer to
state” on page 31
Configuration registers are used to inform applications and operating systems about the setup
and configuration of the processor on which it is running, see
implements the following read-only configuration registers.
Figure 2-8.
Table 2-8 on page 21
Table 2-8.
CONFIG0
CONFIG1
Name
Processor ID
RESERVED
Processor revision
31
31
IMMU SZ
Processor ID
Configuration Registers
CONFIG0 Fields
26
for details.
for details.
Section 4. “Secure state” on page 31
25
Bit
31:24
23:20
19:16
shows the CONFIG0 fields.
24
DMMU SZ
23
for details.
-
Description
Specifies the type of processor. This allows the application to
distinguish between different processor implementations.
Reserved for future use.
Specifies the revision of the processor implementation.
20
20 19
19
Processor
Revision
ISET
16 15
16
15
ILSZ
AT
13 12
13
for details.
12
IASS
AR
Figure 2-8 on page
10
10 9
9
MMUT
DSET
7 6
F
6 5
Section 4. “Secure
Section 4. “Secure
5
J
DLSZ
21. The AVR32
4
P O
AVR32
3 2
3
Section 4.
S
2
DASS
D R
1
0
0
21
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