AT32UC3A4256S Atmel Corporation, AT32UC3A4256S Datasheet - Page 886

• Manufacturer Part Number: AT32UC3A4256S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4256S

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.4.2.3
32.4.3
32072G–11/2011
Last Output Data Mode
DMA mode
The DMA Controller can be used in association with the AES to perform an encryption/decryp-
tion of a buffer without any action by the software during processing.
In this starting mode, the type of the data transfer (byte, halfword or word) depends on the oper-
ation mode.
Table 32-2.
The sequence is as follows:
Note:
Note:
This mode is used to generate cryptographic checksums on data (MAC) by means of cipher
block chaining encryption algorithm (CBC-MAC algorithm for example).
After each end of encryption/decryption, the output data is available either on the ODATAnR
registers for manual and automatic mode or at the address specified in the receive buffer pointer
for DMA mode.
The Last Output Data bit in the Mode Register (MR.LOD) allows retrieval of only the last data of
several encryption/decryption processes.
Therefore, there is no need to define a read buffer in DMA mode.
This data is only available on the Output Data Registers (ODATAnR).
• Write the 128-bit/192-bit/256-bit key in the KEYWnR registers.
• Write the initialization vector (or counter) in the IVnR registers.
• Configure a channel of the DMA Controller with source address (data buffer to
• Enable the DMA Controller in transmission and reception to start the processing.
• The processing completion should be monitored with the DMA Controller.
encrypt/decrypt) and destination address set to register IDATA1R (index is automatically
incremented and rolled over to write IDATAnR). Then configure a second channel with
source address set to ODATA1R (index is automatically incremented and rolled over to read
ODATAnR) and destination address to write processed data.
The Initialization Vector Registers concern all modes except ECB.
Transmit and receive buffers can be identical.
Operation Mode
CFB 128-bit
CFB 64-bit
CFB 32-bit
CFB 16-bit
CFB 8-bit
Data Transfer Type for the Different Operation Modes
ECB
CBC
OFB
CTR
Data Transfer Type (DMA)
halfword
word
word
word
word
word
word
word
byte
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