AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 107
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AT32UC3B0512AU
Manufacturer Part Number
AT32UC3B0512AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A0128AU.pdf
(2 pages)
5.AT32UC3B0128.pdf
(684 pages)
6.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0512AU
Flash (kbytes)
512 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B0512AU-Z2U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
32002F–03/2010
This register is undefined when the CPU is not in Debug Mode.
Table 9-12.
R/W
R
R
R
R
R
R
R
R
R
R
Bit Number
31:29
28
27
26
25
24
23:16
15:8
7:6
5
Development Status register
Field Name
Reserved
NTBF
EXB
DBA
BOZ
INC
Reserved
BP[7:0]
Reserved
DBS
Init. Val.
0
0
0
0
0
0
0
0
0
0
Description
NTBF -NanoTrace Buffer Full
This bit is set if Debug Mode is entered because
the Memory Service Unit has signalled that the
NanoTrace Buffer is full. This bit is cleared when
Debug Mode is exited.
EXB -External Breakpoint
This bit is set if Debug Mode was entered due to
an event on the EVTI pin. This bit is cleared when
Debug Mode is exited.
DBA - Debug Acknowledge
This bit is set if Debug Mode was entered due to
setting the Debug Request or ABORT bit in the
DC register. This bit is cleared when Debug Mode
is exited.
BOZ - Break on Opcode Zero
This bit is set if Debug Mode was entered due to
opcode 0x0000 being executed. This bit is cleared
when Debug Mode is exited.
INC - Instruction Complete
0: The CPU is executing one or more instructions,
or is not in OCD Mode.
1: The CPU is in OCD Mode and is not executing
any instructions.
BP - Breakpoint Status
The BP bits identify which hardware breakpoint
caused Debug Mode to be entered:
BP[0]: BP0A
BP[1]: BP0B
BP[2]: BP1A
BP[3]: BP1B
BP[4]: BP2A
BP[5]: BP2B
BP[6]: BP3A
BP[7]: BP3B
These bits are cleared when Debug Mode is
exited.
DBS - Debug Status
DBS is set when the CPU is in OCD Mode,
otherwise cleared. This bit stays cleared also
when the CPU operates in Monitor Mode.
AVR32
107