AT32UC3C0128C Atmel Corporation, AT32UC3C0128C Datasheet - Page 47
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AT32UC3C0128C
Manufacturer Part Number
AT32UC3C0128C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0128C
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3C0128C-ALUT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
6.1.3.2
32117CS–AVR-08/11
3.3V Single Supply Mode
The 3.3V regulator is connected to the 5V source (VDDIN_5 pin) and its output feeds the USB
pads. If the USB is not used, the 3.3V regulator can be disabled through the VREG33CTL field
of the VREGCTRL SCIF register.
Figure 6-1 on page 47
I/O lines and analog blocks will be powered by the same power (VDDIN_5 = VDDIO1 = VDDIO2
= VDDIO3 = VDDANA).
Figure 6-1.
In 3.3V single supply mode, the VDDIN_5 and VDDIN_33 pins should be connected together
externally. The 1.8V internal regulator is connected to the 3.3 V source (VDDIN_5 pin) and its
output feeds VDDCORE.
The 3.3V regulator should be disabled once the circuit is running through the VREG33CTL field
of the VREGCTRL SCIF register.
Figure 6-2 on page 48
I/O lines and analog blocks will be powered by the same power (VDDIN_5 = VDDIN_33 =
VDDIO1 = VDDIO2 = VDDIO3 = VDDANA).
C
IN2
C
C
OUT2
OUT2
GNDCORE
VDDCORE
VDDIN_33
C
IN1
5V Single Power Supply mode
5.5V
C
C
4.5-
OUT1
OUT1
+
-
shows the power schematics to be used for 3.3V single supply mode. All
shows the power schematics to be used for 5V single supply mode. All
VDDIO1
VDDIO2
VDDIO3
BOD33
BOD18
BOD50
POR
3.3V
1.8V
Reg
Reg
VDDIN_5
VDDANA
Analog: ADC, AC, DAC, ...
SCIF, BOD,
Peripherals
Memories
RCSYS
CPU
PLL
GNDANA
AT32UC3C
GNDPLL
GNDIO1
GNDIO2
GNDIO3
47