AT32UC3C0512C Atmel Corporation, AT32UC3C0512C Datasheet - Page 488
AT32UC3C0512C
Manufacturer Part Number
AT32UC3C0512C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0512C
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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- Download datasheet (20Mb)
24.3
24.4
24.4.1
24.4.2
24.4.3
32117C–AVR-08/11
Block Diagram
Product Dependencies
I/O Lines
Power Management
Clocks
Figure 24-1. MACB Block Diagram
In order to use this module, other parts of the system must be configured correctly, as described
below.
The pins used for interfacing the MACB may be multiplexed with the I/O Controller lines. The
programmer must first program the I/O Controller to assign the desired MACB pins to their
peripheral function. If I/O lines of the MACB are not used by the application, they can be used for
other purposes by the I/O Controller.
If the CPU enters a sleep mode that disables clocks used by the MACB, the MACB will stop
functioning and resume operation after the system wakes up from sleep mode.
To prevent bus errors the MACB operation must be terminated before entering sleep mode.
The clocks for the MACB bus interface (CLK_MACB_PB/CLK_MACB_HSB) are generated by
the Power Manager. These clocks are enabled at reset, and can be disabled in the Power Man-
High Speed Bus
Peripheral Bus
Master
Slave
RX FIFO
Register Interface
DMA Interface
TX FIFO
Statistics Registers
Ethernet Transmit
Address Checker
Control Registers
Ethernet Receive
AT32UC3C
MII/RMII
MDIO
488
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