AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 155
AT32UC3C0512CAU
Manufacturer Part Number
AT32UC3C0512CAU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3A0128AU.pdf
(2 pages)
4.AT32UC3C0128C.pdf
(1313 pages)
5.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0512CAU
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
10. Revision History
32002F–03/2010
Doc. Rev.
32002F
32002E
32002D
32002C
32002B
32002A
Date
2009-08-01
2007-11-19
2007-03-30
2010-03-12
2009-09-01
2007-08-03
Comments
Improved description of events and priority.
Replaced invalid reference in the OCD.PDBG register.
Note added about overall system interrupt latency.
Added MSU system registers.
Added Floating-Point hardware description.
Added OCD DCCPU and DCEMU interrupts.
Added PDBG register for individual module masks.
Added AVR32 architecture revision 3 secure state support.
COUNT/COMPARE system register reset-on-match now programmable by CPUCR
Corrected LDM, STM, and SCALL instruction cycle count in cycle count chapter.
Corrected maximum IRQ latency in the Pipeline chapter.
MPU compilant with revision 2 of AVR32 Architecture.
Added cycle counts for new instruction in version 2 of the CPU.
Added COUNT/COMPARE system register reset-on-match.
Added CPU Local Bus.
Reconfigured OCD AXC register.
Added Memory Service Unit (MSU) description. Added description of peripheral behavior
in Debug.
Initial revision.
AVR32
155