AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 1282
AT32UC3C0512CAU
Manufacturer Part Number
AT32UC3C0512CAU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3A0128AU.pdf
(2 pages)
4.AT32UC3C0128C.pdf
(1313 pages)
5.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0512CAU
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128AU PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
- AT32UC3C0128C PDF datasheet #5
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Table 40-58. SDRAM Signal
Note:
32117C–AVR-08/11
Symbol
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
23
24
25
26
cess technology. These values are not covered by test limits in production.
Parameter
SDCKE high before SDCK rising edge
SDCKE low after SDCK rising edge
SDCKE low before SDCK rising edge
SDCKE high after SDCK rising edge
SDCS low before SDCK rising edge
SDCS high after SDCK rising edge
RAS low before SDCK rising edge
RAS high after SDCK rising edge
SDA10 change before SDCK rising edge
SDA10 change after SDCK rising edge
Address change before SDCK rising edge
Address change after SDCK rising edge
Bank change before SDCK rising edge
Bank change after SDCK rising edge
CAS low before SDCK rising edge
CAS high after SDCK rising edge
DQM change before SDCK rising edge
DQM change after SDCK rising edge
D0-D15 in setup before SDCK rising edge
D0-D15 in hold after SDCK rising edge
SDWE low before SDCK rising edge
SDWE high after SDCK rising edge
D0-D15 Out valid before SDCK rising edge
D0-D15 Out valid after SDCK rising edge
(1)
drive strength of the pads set to
external capacitor = 40pF on
except 8 pF on SDCK pins
SDRAM pins
V
Conditions
the highest,
VDD
= 3.0V,
Min
AT32UC3C
8.4
6.4
5.6
5.6
7.3
6.8
8.3
6.1
7.7
7.1
4.7
4.4
6.2
6.9
6.6
7.8
6.7
6.4
7.4
5.2
7
6
0
7
Units
ns
1282
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