AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 240
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AT32UC3C0512CAU
Manufacturer Part Number
AT32UC3C0512CAU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3A0128AU.pdf
(2 pages)
4.AT32UC3C0128C.pdf
(1313 pages)
5.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0512CAU
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128AU PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
- AT32UC3C0128C PDF datasheet #5
- Current page: 240 of 377
- Download datasheet (5Mb)
240
AVR32
MULSATRNDWH.W – Multiply Word and Halfword with Saturation and
Rounding into Word
Architecture revision:
Architecture revision1 and higher.
Description
Multiplies the word register with the halfword register specified, rounds the upper 32 bits of the
result and stores it in the destination word-register. The halfword register is selected as either
the high or low part of Ry. Since the most significant part of the product is stored, no overflow will
occur. If the two operands equals -1, the result is saturated to the largest positive 32-bit fractional
number.
Operation:
I.
Syntax:
I.
Operands:
I.
Status Flags:
Opcode:
Example:
0x4000) >> 15
31
1
15
0
operand1 = Rx;
If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]);
If ((operand1 == 0x8000_0000) && (operand2 == 0x8000))
else
mulsatrndwh.w Rd, Rx, Ry:<part>
{d, x, y} ∈ {0, 1, …, 15}
part ∈ {t,b}
Q:
V:
N:
Z:
C:
mulsatrndwh.w R10, R2, R3b will perform R10 ← (Sat( R2[31:16] × SE(R3[15:0]) ) +
1
0
29
1
0
Rd ← 0x7FFF_FFFF;
Rd ← SE( ((operand1 × operand2) + 0x4000 ) >> 15 );
Set if saturation occurred, or previously set.
Not affected.
Not affected.
Not affected.
Not affected.
12
28
0
11
1
Rx
0
25
1
8
24
0
1
7
0
1
0
0
5
0
0
4
Y
20
0
3
19
Ry
Rd
32000D–04/2011
0
16
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