AT32UC3C064C Atmel Corporation, AT32UC3C064C Datasheet - Page 414
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AT32UC3C064C
Manufacturer Part Number
AT32UC3C064C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C064C
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
- Current page: 414 of 1313
- Download datasheet (20Mb)
21.6.3
21.6.4
32117C–AVR-08/11
Adding Descriptors to a List
Interrupts in Descriptor Mode
Figure 21-2. Descriptors in Memory
In order to add descriptors to a list, the following actions must be performed:
Interrupt on transfer complete and bus error can be enabled as described in
1. Check if there are free entries in the list for the desired channel. Any entry with the V bit
2. Find the first free entry in the list. This can be done by scanning the descriptor list from
3. Update the free entry by writing the desired values to the correct memory locations.
4. Make sure the CHxM bit for the channel is one (channel is in Descriptor Mode), and
cleared is free. If no entries are free, wait until an entry becomes free.
the entry pointed to by CDARx downto the first descriptor with the V bit cleared.
write a one to the CHxEN bit. Writing a one to CHxEN when the CHxEN bit is one has
no effect, so the user does not need to check the state of CHxEN before adding
descriptors to the list.
UNUSED
UNUSED
UNUSED
D0 WAR
D1 WAR
Dn WAR
D0 CCR
D1 CCR
Dn CCR
D0 RAR
D1 RAR
Dn RAR
Last bit set
DSAR
AT32UC3C
Section
21.4.5.
414
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