AT32UC3C1256C Atmel Corporation, AT32UC3C1256C Datasheet - Page 1075
AT32UC3C1256C
Manufacturer Part Number
AT32UC3C1256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C1256C
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C1256C-AUR
Manufacturer:
LORLIN
Quantity:
1 000
Company:
Part Number:
AT32UC3C1256C-AUT
Manufacturer:
ATMEL
Quantity:
1 001
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35.4
35.4.1
35.4.2
35.4.3
35.4.4
35.4.5
35.5
35.5.1
35.5.1.1
32117C–AVR-08/11
Product Dependencies
Functional Description
Power Management
Clocks
Interrupts
Peripheral Events
Debug Operation
Normal mode
ACIFA Output
In order to use this module, other parts of the system must be configured correctly, as described
below.
When the ACIFA is enabled it will remain clocked as long as its selected clock source is running.
It can also wake the CPU from the currently active sleep mode. Refer to the Power Manager
chapter for details on the different sleep modes.
The clock for the ACIFA bus interface (CLK_ACIFA) is generated by the Power Manager. this
clock is turned on by default, and can be enabled and disabled in the Power Manager.
The ACIFA interrupt request lines are connected to the interrupt controller. Using the ACIFA
interrupts requires the Interrupt Controller to be programmed first.
The ACIFA peripheral events are connected via the Peripheral Event System. Refer to the
Peripheral Event System chapter for details.
The ACIFA is frozen during debug operation, unless the Run In Debug bit in the Development
Control Register is set and the bit corresponding to the ACIFA is set in the Peripheral Debug
Register (PDBG). Please refer to the On-Chip Debug chapter in the AVR32UC Technical Refer-
ence Manual, and the OCD Module Configuration section, for details.
In normal mode, both analog comparators are independent.
An analog comparator generates one output acout[i] (with i = a or b) according to the input volt-
ages vip
The ACIFA generates two independent events according to the configuration of the Event
Source Selection field in the Event Configuration register (EVSRC0.EVSRC and
EVSRC1.EVSRC):
• acout[i] = 1 if vip
• acout[i] = 0 if vip
• acout[i] = 0 if the AC output is not available (ie. The AC Ready bit in the Status Register
• as soon as vipA > vinA or
• as soon as vipA < vinA or
• as soon as vipB > vinB or
(SR.ACRDYi) is still zero)
i
(AC positive input) and vin
i
i
> vin
< vin
i
i
i
(AC negative input):
AT32UC3C
1075
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