AT32UC3C1512C Atmel Corporation, AT32UC3C1512C Datasheet - Page 56
AT32UC3C1512C
Manufacturer Part Number
AT32UC3C1512C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C1512C
Flash (kbytes)
512 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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- Download datasheet (20Mb)
32117C–AVR-08/11
Figure 7-3.
In addition to the listed reset types, the JTAG & AWIRE can keep parts of the device statically
reset. See JTAG and AWIRE documentation for details.
Table 7-4.
When a Reset occurs, some parts of the chip are not necessarily reset, depending on the reset
source. Only the Power On Reset (POR) will force a reset of the whole chip. Refer to the module
configuration chapter to know the effect of the different reset events.
The table located in the module configuration chapter lists parts of the device that are reset,
depending on the reset source.The cause of the last reset can be read from the RCAUSE regis-
ter. This register contains one bit for each reset source, and can be read during the boot
sequence of an application to determine the proper action to be taken.
Reset source
Power-on Reset
External Reset
Brownout Reset
CPU Error
Watchdog Timer
OCD
R E S ET _N
P ow er-O n
B row nout
D etector
D etector
W atchdog R eset
Reset Controller Block Diagram
Reset Description
AW IR E
JTAG
O C D
Description
Supply voltage below the power-on reset detector threshold
voltage
RESET_N pin asserted
Supply voltage on VDDCORE below the brownout reset
detector threshold voltage
Caused by an illegal CPU access to external memory while
in Supervisor mode
See Watchdog Timer documentation.
See On-Chip Debug documentation
R C _R C A U SE
C ontroller
R eset
O C D , AST, W D T,
C P U , H S B , P B x
C lock G enerator
AT32UC3C
56
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