AT32UC3L0128 Atmel Corporation, AT32UC3L0128 Datasheet - Page 737

• Manufacturer Part Number: AT32UC3L0128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

31. Programming and Debugging
31.1
31.2
31.2.1
32145A–12/2011
Overview
Service Access Bus
SAB Address Map
The AT32UC3L0128/256 supports programming and debugging through two interfaces, JTAG
or aWire. JTAG is an industry standard interface and allows boundary scan for PCB testing, as
well as daisy-chaining of multiple devices on the PCB. aWire is an Atmel proprietary protocol
which offers higher throughput and robust communication, and does not require application pins
to be reserved. Either interface provides access to the internal Service Access Bus (SAB), which
offers a bridge to the High Speed Bus, giving access to memories and peripherals in the device.
By using this bridge to the bus system, the flash and fuses can thus be programmed by access-
ing the Flash Controller in the same manner as the CPU.
The SAB also provides access to the Nexus-compliant On-chip Debug (OCD) system in the
device, which gives the user non-intrusive run-time control of the program execution. Addition-
ally, trace information can be output on the Auxiliary (AUX) debug port or buffered in internal
RAM for later retrieval by JTAG or aWire.
The AVR32 architecture offers a common interface for access to On-chip Debug, programming,
and test functions. These are mapped on a common bus called the Service Access Bus (SAB),
which is linked to the JTAG and aWire port through a bus master module, which also handles
synchronization between the debugger and SAB clocks.
When accessing the SAB through the debugger there are no limitations on debugger frequency
compared to chip frequency, although there must be an active system clock in order for the SAB
accesses to complete. If the system clock is switched off in sleep mode, activity on the debugger
will restart the system clock automatically, without waking the device from sleep. Debuggers
may optimize the transfer rate by adjusting the frequency in relation to the system clock. This
ratio can be measured with debug protocol specific instructions.
The Service Access Bus uses 36 address bits to address memory or registers in any of the
slaves on the bus. The bus supports sized accesses of bytes (8 bits), halfwords (16 bits), or
words (32 bits). All accesses must be aligned to the size of the access, i.e. halfword accesses
must have the lowest address bit cleared, and word accesses must have the two lowest address
bits cleared.
The SAB gives the user access to the internal address space and other features through a 36
bits address space. The 4 MSBs identify the slave number, while the 32 LSBs are decoded
within the slave’s address space. The SAB slaves are shown in
Table 31-1.
Unallocated
Slave
OCD
HSB
SAB Slaves, Addresses and Descriptions
Address [35:32]
0x0
0x1
0x4
Description
Intentionally unallocated
OCD registers
HSB memory space, as seen by the CPU
AT32UC3L0128/256
Table
31-1.
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