AT32UC3L032 Atmel Corporation, AT32UC3L032 Datasheet - Page 52
AT32UC3L032
Manufacturer Part Number
AT32UC3L032
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3L016.pdf
(843 pages)
4.AT32UC3L016.pdf
(110 pages)
Specifications of AT32UC3L032
Flash (kbytes)
32 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
4
Lin
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3L032-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
7.7.3
Table 7-14.
Notes:
32099G–06/2011
Symbol
f
f
I
t
t
OUT
REF
DFLL
STARTUP
LOCK
1. Spread Spectrum Generator (SSG) is disabled by writing a zero to the EN bit in the SCIF.DFLL0SSG register.
2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
Digital Frequency Locked Loop (DFLL) Characteristics
cess technology. These values are not covered by test limits in production.
Digital Frequency Locked Loop Characteristics
Parameter
Output frequency
Reference frequency
FINE resolution
Frequency drift over voltage
and temperature
Accuracy
Power consumption
Startup time
Lock time
(2)
(2)
(2)
(2)
Conditions
FINE > 100, all COARSE values
Fine lock, f
Accurate lock, f
RCSYS/2, SSG disabled
Fine lock, f
disabled
Accurate lock, f
clk RCSYS/2, SSG disabled
Within 90% of final values
f
f
clock = RCSYS/2, SSG disabled
REF
REF
= 32kHz, fine lock, SSG disabled
= 32kHz, accurate lock, dithering
REF
REF
= 8-150kHz, SSG
= 32kHz, SSG disabled
REF
REF
= 32kHz, dither clk
= 8-150kHz, dither
AT32UC3L016/32/64
Min
40
8
Figure 7-4
1100
0.25
0.06
Typ
See
600
0.1
0.2
0.1
22
Max
150
150
100
0.5
0.5
1
1
µA/MHz
Unit
MHz
kHz
µs
%
%
52