AT83EB5114 Atmel Corporation, AT83EB5114 Datasheet
AT83EB5114
Specifications of AT83EB5114
Related parts for AT83EB5114
AT83EB5114 Summary of contents
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... The prescaler allows to decrease CPU and periph- erals clock frequency. The fully static design of the AT8xEB5114 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. Low-pin-count 8-bit microcontroller with A/D converter AT83EB5114 AT89EB5114 Rev. 4311C–8051–02/08 1 ...
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Figure 1. Block Diagram XTAL1 Xtal Osc XTAL2 R RC CPU Osc C (12 MHz) RC Timer 0 Osc Timer 1 (12 MHz) (2) (2) (3) AT89/83EB5114 2 The AT8xEB5114 has 3 software-selectable modes of reduced activity for further reduc- ...
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Pin Configuration 4311C–8051–02/08 P4.0/AIN0/W0CI P4.1/AIN1/ P4.2/AIN2/W1CI 3 17 P4.3/AIN3/INT1 4 P3.3/W0M2/AIN4 16 5 SO20 P3.4/T0/AIN5 P3.5/W1M0 P3.2/INT0 9 P3.1/W0M1 12 P3.0/W0M0 10 11 VRef P4.0/AIN0/W0CI 1 Vcca P4.1/AIN1/T1 2 ...
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Pin Description SO20 SO24 Mnemonic Vssa Vcca 20 24 VREF 14 17 XTAL1 15 18 XTAL2 RST P3.0-P3 ...
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SFR Mapping 4311C–8051–02/08 The Special Function Registers (SFRs) of the AT8xEB5114 belong to the following categories: • C51 core registers: ACC, AUXR, AUXR1, B, DPH, DPL, PSW, SP, FCON, HSB • I/O port registers: P3, P4, P3M1, P3M2, P4M1 • ...
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Table 1. SFR Addresses and Reset Values 0/8 1/9 W1CON F8h XXX0 0000 B F0h 0000 0000 W0CON W0MOD E8h 00XX 0000 00XX X000 ACC E0h 0000 0000 W0R0H D8h 0000 0000 FCON PSW D0h 0000 0000 1111 1111 W1R0H ...
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Mnemonic Add Name ACC E0h Accumulator ADCA F7h ADC Amplifier Configuration ADCF F6h ADCF Register ADCLK F2h ADC Clock Prescaler ADCON F3h ADC Control Register ADDH F5h ADC Data High Byte Register ADDL F4h ADC Data Low Byte Register AUXR ...
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Mnemonic Add Name TMOD 89h Timer/Counter Mode Register W0CH ECh PWMU0 Counter High Control W0CL EDh PWMU0 Counter Low Control W0CON E8h PWMU0 Control Register PWMU0 Frequency High W0FH EAh Control PWMU0 Frequency Low W0FL EBh Control W0IC EEh PWMU0 ...
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Power Monitor Description Figure 2. Power Monitor Block Diagram External Vcc Power-Supply Power Monitor diagram 4311C–8051–02/08 The Power Monitor function supervises the evolution of the voltages feeding the micro- controller, and if needed, suspends its activity when the detected value ...
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Figure 3. Power-Up and Steady-state Conditions Monitored Vcc VPFDP VPFDM tG tR Power-up Reset Vcc AT89/83EB5114 10 Steady State Condition The POR/PFD forces the CPU into reset mode when VCC reaches a voltage condition which is out of specification. The ...
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Clock System Overview Blocks Description Figure 4. Functional Block Diagram Xtal1 Xtal_Osc OSCA Xtal2 OSCAEN OSCBEN PwdOsc RC_Osc R OSCB C Freq. Adjust LCKEN RC_Osc OSCC OSCCEN 4311C–8051–02/08 The AT8xEB5114 oscillator system provides a reliable clocking system with full master- ...
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Crystal Oscillator: OSCA High Accurate RC Oscillator: OSCB Low Power Consumption Oscillator: OSCC Clock Selector X2 Feature AT89/83EB5114 12 The crystal oscillator uses two external pins, XTAL1 for input and XTAL2 for output. OSCAEN in OSCCON register is an enable ...
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Description Figure 5. Mode Switching Waveforms XTAL1 XTAL1:2 X2 bit CPU clock STD Mode Clock Prescaler Prescaler Divider on Reset 4311C–8051–02/08 The clock for the whole circuit and peripherals is first divided by two before being used by the CPU ...
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AT89/83EB5114 14 Some examples can be found in the table below: F OscOut MHz • A software instruction which set X2 bit disables the prescaler/divider, so the internal clock is either OSCA, OSCB ...
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Registers Hardware Security Byte 4311C–8051–02/08 The security byte sets the starting microcontroller options and the security levels. The default options are X1 mode, Oscillator A and divided by 16 prescaler. Table 2. Hardware Security Byte (HSB) Power configuration Register - ...
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Clock Control Register Oscillator B Frequency Adjust Register AT89/83EB5114 16 The clock control register is used to define the clock system behavior. Table 3. OSCON Register OSCCON - Clock Control Register (86h OSCARY Bit Bit ...
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Clock Selection Register 4311C–8051–02/08 Table 4. OSCBFA Register OSCBFA- Oscillator B Frequency Adjust Register (9Fh OSCBFA7 OSCBFA6 OSCBFA5 Bit Bit Number Mnemonic Description OSCB Frequency adjust OSCBFA 7-0 The reset value to have 12 MHz is 0111 ...
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Clock Prescaler Register Clock Control Register AT89/83EB5114 18 This register is used to reload the clock prescaler of the CPU and peripheral clock. Table 6. CKRL Register CKRL - Clock prescaler Register (97h Bit ...
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Power Modes Overview Operating Modes Normal Mode Idle Mode Entering Idle Mode 4311C–8051–02/08 As seen in the previous chapter it is possible to modify the AT8xEB5114 clock manage- ment in order to have less consumption. For applications where power consumption ...
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Exit from Idle Mode Quiet Mode Power-down Mode Entering Power-down Mode Exit from Power-down Mode Figure 6. Power-down Exit Waveform INTERRUPT OSC Active phase AT89/83EB5114 20 their data during Idle. The port pins hold the logical states they had at ...
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Table 10. Operating Modes PD IDLE CKS1 CKS0 ...
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Power Modes Control Registers AT89/83EB5114 22 Table 11. PCON Register PCON (S:87h) Power configuration Register Bit Bit Number Mnemonic Description 7 Reserved 6 Reserved 5 Reserved 4 Reserved General Purpose flag 1 3 GF1 ...
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AUXR Register 4311C–8051–02/08 Table 12. AUXR Register AUXR - Auxiliary Register (8Eh DPU - - Bit Bit Number Mnemonic Description Disable Pull up Set to disable each pull up on all ports. 7 DPU Clear to connect ...
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Timers/Counters Introduction Timer/Counter Operations Timer 0 AT89/83EB5114 24 The AT8xEB5114 implements two general-purpose, 16-bit Timers/Counters. Although they are identified as Timer 0, Timer 1, they can be independently configured each to operate in a variety of modes as a Timer ...
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Mode 0 (13-bit Timer) Figure 7. Timer/Counter x ( Mode 0 F CkIdle / 6 Tx C/Tx# TMOD reg INTx# GATEx TMOD reg Mode 1 (16-bit Timer) Figure 8. Timer/Counter ...
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Figure 9. Timer/Counter Mode 2 F CkIdle / 6 Tx C/Tx# TMOD reg INTx# GATEx TMOD reg Mode 3 (Two 8-bit Timers) Figure 10. Timer/Counter 0 in Mode 3: Two 8-bit Counters F ...
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Mode 0 (13-bit Timer) Mode 1 (16-bit Timer) Mode 2 (8-bit Timer with Auto- Reload) Mode 3 (Halt) 4311C–8051–02/08 • For normal Timer operation (GATE1= 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and ...
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Registers AT89/83EB5114 28 Table 13. TCON (S:88h) Timer/Counter Control Register TF1 TR1 TF0 Bit Bit Number Mnemonic Description Timer 1 Overflow flag 7 TF1 Cleared by the hardware when processor vectors to interrupt routine. Set by the ...
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Table 14. IOR (S:A5h) Interrupt Option Register Bit Bit Number Mnemonic Description Reserved 7-2 - The value read from this bit is indeterminate. Do not set this bit. Edge Selection bit for INT1 ...
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AT89/83EB5114 30 Table 15. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register GATE1 C/T1# M11 Bit Bit Number Mnemonic Description Timer 1 Gating Control bit 7 GATE1 Clear to enable Timer counter 1 whenever TR1 bit is ...
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Table 17. TL0 Register TL0 (S:8Ah) Timer 0 Low Byte Register Bit Bit Number Mnemonic Description 7:0 Low Byte of Timer 0. Reset Value = 0000 0000b Table 18. TH1 Register TH1 (S:8Dh) Timer 1 High ...
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Ports Port Types Quasi-Bidirectional Output Configuration AT89/83EB5114 32 The AT8xEB5114 has 2 I/O ports, port 3, and port 4. All port3 and port4 I/O port pins on the AT8xEB5114 may be software configured to one of four types on a ...
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Figure 11. Quasi-Bidirectional Output Port Latch Data Open Drain Output Configuration Figure 12. Open Drain Output Port latch Data Push-Pull Output Configuration 4311C–8051–02/ CPU CLOCK DELAY N Input Data The open drain output configuration turns off all pull-ups ...
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Figure 13. Push-Pull Output Port latch Data Input only Configuration Ports Description Ports P3 and P4 AT89/83EB5114 34 P Strong N Input Data The input only configuration is a pure input with neither pull-up nor pull-down. The input only configuration ...
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Registers 4311C–8051–02/08 Table 21. P3M1 Register P3M1 Address (D5h P3M1.7 P3M1.6 P3M1.5 Bit Bit Number Mnemonic Description Port 3.3 Output configuration bit 7-6 P3M1.7-6 See Table 20 for configuration definition Port 3.2 Output configuration bit 5-4 P3M1.5-4 ...
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AT89/83EB5114 36 Table 23. P4M1 Register P4M1 Address (D6h P4M1.7 P4M1.6 P4M1.5 Bit Bit Number Mnemonic Description Port 4.3 Output configuration bit 7-6 P4M1.7-6 See Table 20 for configuration definition Port 4.2 Output configuration bit 5-4 P4M1.5-4 ...
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Dual Data Pointer Register (DDPTR) Figure 15. Use of Dual Pointer 7 DPS AUXR1(A2H) 4311C–8051–02/08 The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure ...
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AT89/83EB5114 38 Table 24. AUXR1: Auxiliary Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value ...
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Application 4311C–8051–02/08 Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search...) are well served by using one data pointer as a ’source’ pointer and the ...
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PWM Unit 0 (PWMU0) PWMU0 Timer AT89/83EB5114 40 The PWM unit 0 allows to generate precise pulse width modulation with variable duty cycle and frequency. The PWMU0 consists on a dedicated 16 bits auto reload counter/timer which serves as a ...
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Figure 16. PWMU0 Timer/Counter FCkIdle T0 OVF W0CI W0UP W0R W0PS1 WOPS0 Table 25. W0CON: PWMU0 Control register W0CON - PWMU0 Control Register (E8h W0UP W0R - Bit Bit Number Mnemonic Description PWMU0 update bit 7 ...
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AT89/83EB5114 42 Table 26. W0MOD: PWMU0 Counter Mode Register W0MOD - PWMU0 Counter Mode Register (E9h W0CPS1 W0CPS0 - Bit Bit Number Mnemonic Description 7 W0CPS1 PWMU0 Count Pulse Select bit1 PWMU0 Count Pulse Select bit0 CPS1 ...
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PWMU0 Output Generation 4311C–8051–02/08 Table 28. W0FL: PWMU0 frequency low control register W0FL - PWMU0 Frequency Control Register (EBh W0F7 W0F6 W0F5 Bit Bit Number Mnemonic Description PWMU0 low bits counter control frequency 7-0 W0F7-0 The PWMU0 ...
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AT89/83EB5114 44 content of the W0R0 registers (see Figure 16). This method allows to change frequency and duty cycle without glitch. Note: If the PWMU0 is off (W0R bit in W0CON not set), W0RnH and W0RnL contents are auto- matically ...
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PWMU0 Output Selector PWMU0 Interrupt System 4311C–8051–02/08 Table 32. W0RnL: PWMU0 module n Low Toggle Register W0R0L - PWMU0 Module 0 Low Toggle Register (DAh) W0R1L - PWMU0 Module 1 Low Toggle Register (DCh) W0R2H - PWMU0 Module 2 Low ...
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AT89/83EB5114 46 Figure 19. PWMU0 Interrupt Configuration Module 0 Module 1 Module 2 Overtaking COF CF2 CF1 CF0 ECOF ECF2 W0IC Table 33. PWMU0 interrupt control register W0IC - PWMU0 Interrupt Control Register (EEh) 7 ...
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PWM Unit 1 (PWMU1) PWMU1 Timer 4311C–8051–02/08 The PWM unit 1 allows to generate precise pulse width modulation with variable duty cycle and frequency. The PWMU1 consists of a dedicated 16 bits auto reload counter/timer which serves as a time ...
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AT89/83EB5114 48 Figure 20. PWMU1 Timer/Counter FCkIdle T0 OVF W1CI W1UP W1R 0000 0000 16 bit up counter W1CH W1CL 16 bit comparator Š SW1FH SW1FL W1FH W1FL W1CON W1OCLKW1CPS1 W1CPS0 W1INV0 W1EN0 4311C–8051–02/08 To PWMU1 modules overtaking ...
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Table 34. W1CON: PWMU1 Control Register W1CON - PWMU1 Control Register (F8h W1UP W1R - Bit Bit Number Mnemonic Description PWMU1 update bit Set by software to request the load of all shadow registers on the ...
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PWMU1 Output Generation AT89/83EB5114 50 Table 36. W1FL: PWMU1 frequency low control register W1FL - PWMU1 Frequency Control Register (FBh W1F7 W1F6 W1F5 Bit Bit Number Mnemonic Description PWMU1 low bits counter control frequency 7-0 W1F7-0 The ...
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W1R0 registers (see Figure 21.). This method allows to change frequency and duty cycle without glitch. Note: If the PWMU1 is Off (W1R bit in W0CON not set), W1RnH and W1RnL contents are automatically copied on ...
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PWMU1 Output Selector PWMU1 Interrupt System AT89/83EB5114 52 As shown on Figure 22., the PWMU1 can configure P3 used as • The PWMU1 module 0 output (W1R = 1 and W1EN0 = 1) • The External Clocking output ...
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Table 41. PWMU1 Interrupt Control Register W1IC - PWMU1 Interrupt Control Register (FEh W1CF - - Bit Bit Number Mnemonic Description PWMU1 Counter Overtaking Flag Set by hardware when the counter rolls over. CF flags an ...
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WatchDog Timer Figure 24. WatchDog Timer RESET F CPU_PERIPH - - AT89/83EB5114 54 AT8xEB5114 contains a powerful programmable hardware WatchDog Timer (WDT) that automatically resets the chip if its software fails to reset the WDT before the selected time interval ...
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Figure 25. WDTPRG Register WDTPRG - WatchDog Timer Duration Programming register (A7h). Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read ...
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WatchDog Timer During Power Down Mode and Idle AT89/83EB5114 56 Find Hereafter computed Time-Out value for Fosc = 12 MHz Table 42. Time-Out Computation @12 MHz ...
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Analog-to-Digital Converter (ADC) Features 4311C–8051–02/08 This section describes the on-chip 10 bit analog-to-digital converter of the AT8xEB5114. Six ADC channels are available for sampling of the external sources AIN0 to AIN5. An analog multiplexer allows the single ADC converter to ...
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ADC I/O Functions Figure 26. ADC Description CONV_CK AIN0/P4.0 000 AIN1/P4.1 001 AIN2/P4.2 010 AIN3/P4.3 011 100 AIN4/P3.3 AIN5/P3.4 101 R * gain ADCA.2 SCH2 AC3E ADCON.2 Figure 27. Timing Diagram CONV_CK ADEN T SETUP ADSST ADEOC Note: Tsetup = ...
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Channel 3 Amplifier and Rectifying Function ADCA (S:F7h) ADC Amplifier Configuration 4311C–8051–02/08 If needed, the average value of the rectified signal on channel 3 can be extracted and amplified before A/D conversion as shown on Figure 28. Figure 28. Channel ...
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ADC Converter Operation Voltage Conversion Clock Selection AT89/83EB5114 60 A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). The busy flag ADSST(ADCON.3) remains set as long as an A/D conversion is running. After completion of the ...
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ADC Standby Mode Voltage Reference IT ADC Management 4311C–8051–02/08 Figure 29. A/D Converter clock CKADC / 2 The conversion frequency CONV_CK is derived from the oscillator frequency with the following formulas (32 - 2*CKRL), if X2=0 ...
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Accuracy improvement on analog to digital conversion using the internal voltage reference Overview Coefficient address Coefficient format True Vref Value (V) Value stored decimal value AT89/83EB5114 62 The internal Vref absolute accuracy is around 4%. This variation is mainly due ...
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How to Take Advantage of the Calibration Value Example Assembler code example Registers 4311C–8051–02/08 The coefficient stored on the stacked die allow to determine the conversion result the AT8xEB5114 should have returned in case its Vref was exactly equal to ...
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AT89/83EB5114 64 Bit Bit Number Mnemonic Description Enable/Standby Mode 5 ADEN Set to enable ADC. Clear for Standby mode. End Of Conversion Set by hardware when ADC result is ready to be read. This flag can generate an 4 ADEOC ...
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Table 51. ADDL Register ADDL (S:F4h Read Only) ADC Data Low byte register Bit Bit Number Mnemonic Description Reserved 7-6 - The value read from these bits are indeterminate. Do not set these ...
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AT89/83EB5114 66 Table 52. ADCF Register ADCF (S:F6h) ADC Configuration CH5 Bit Bit Number Mnemonic Description 7-6 - Not used Channel Configuration Set to use P3.4 as ADC input 5 CH5 Clear to use P3.4 ...
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Interrupt System Figure 31. Interrupt Control System INT0 IE0 0 1 ESB0 TF0 INT1 IE1 0 1 ESB1 TF1 PWMU0 PWMU1 ADC 4311C–8051–02/08 The AT8xEB5114 has a total of 8 interrupt vectors: two external interrupts (INT0 and INT1), two timer ...
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AT89/83EB5114 68 Table 53. Priority Bit Level Values IPH low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt ...
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Table 54. IEN0 Register IEN0 - Interrupt Enable Register (A8h EADC EW1 Bit Bit Number Mnemonic Description Enable All interrupt bit setting or clearing its interrupt enable bit. ADC Interrupt Enable 6 ...
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AT89/83EB5114 70 Table 55. IPL0 Register IPL0 - Interrupt Priority Register (B8h PADC PW1 Bit Bit Number Mnemonic Description Reserved 7 - ADC interrupt Priority bit 6 PADC PWMU1 Priority bit 5 PW1 PWMU0 Priority bit ...
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Table 56. IPH0 Register IPH0 - Interrupt Priority High Register (B7h PADCH PW1H Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ADC Interrupt ...
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Flash Memory FM0 Memory Architecture User Space Extra Row (XRow) Hardware security Byte Column latches Overview of Flash Memory Operations AT89/83EB5114 72 As shown Figure 32, the Flash version of AT8xEB5114 implements 4 Kbytes of on-chip program/code memory. The Flash ...
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Mapping of the Memory Space Launching programming 4311C–8051–02/08 – Launch the programming of the memory spaces – Get the status of the flash memory (busy/not busy) By default, the user space is accessed by MOVC instruction for read only. The ...
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Status of the Flash Memory Loading the Column Latches AT89/83EB5114 74 The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress. Any number of data from 1 byte ...
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Programming the Flash Spaces 4311C–8051–02/08 User The following procedure is used to program the User space and is summarized in Figure 35: – Load data in the column latches from address 0000h to 0FFFh – Disable the interrupts. – Launch ...
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AT89/83EB5114 76 Figure 35. Flash and Extra row Programming Procedure Column Latches Loading Hardware Security Byte The following procedure is used to program the Hardware and is summarized in Figure 36: – Set FPS and map Hardware byte (FCON = ...
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Reading the Flash Spaces 4311C–8051–02/08 Figure 36. Hardware Programming Procedure Flash Spaces Programming Exec: MOVX @DPTR, A Launch Programming User The following procedure is used to read the User space and is summarized in Figure 37: – Map the User ...
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Flash Protection from Parallel Programming AT89/83EB5114 78 The following procedure is used to read the Hardware summarized in Figure 37: – Map the Hardware Security space by writing 04h in FCON register. – Read the byte in Accumulator by executing ...
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Registers 4311C–8051–02/08 Table 59. FCON: Flash Control Register FCON - Flash Control Register (D1h FPL3 FPL2 FPL1 Bit Bit Number Mnemonic Description Programming Launch Command Bits 7-4 FPL3:0 Write 5Xh followed by AXh to launch the programming ...
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AT8xEB5114 ROM ROM Structure Hardware Configuration Byte AT89/83EB5114 80 The AT8xEB5114 ROM memory is divided in two different arrays: • the code array: 4 Kbytes. • the configuration byte:1 byte. The configuration byte sets the starting microcontroller options and the ...
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ROM Lock System Program ROM lock Bits 4311C–8051–02/08 The program Lock system, when programmed, protects the on-chip program against software piracy. The lock bits when programmed according to Table 61 will provide different level of pro- tection for the on-chip ...
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AT89/83EB5114 82 4311C–8051–02/08 ...
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Stacked EEPROM Overview Protocol 4311C–8051–02/08 The AT8xEB5114 features a stacked 2-wire serial data EEPROM. The data EEPROM allows to save up to 256 bytes. The EEPROM is internally connected to P3.6 and P3.7 which are respectively connected to the SDA ...
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Electrical Characteristics Absolute Maximum Ratings Ambient Temperature Under Bias commercial..................................................... 0°C to 70° industrial ....................................................... -40°C to 85°C Storage Temperature ................................... -65° 150°C Voltage .....................................-0 4.6 V ...
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Table 1. DC Parameters for Low Voltage (Continued) Symbol Parameter V Output High Voltage, ports 3, 4. OH2 I Logical 0 Input Current ports 3 and Input Leakage Current IL I Logical Transition Current, ...
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Table 1. DC Parameters for Low Voltage (Continued) Symbol Parameter t Supply rise time R Notes under reset is measured with all output pins disconnected; XTAL1 driven with 0 ...
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Figure 40. I Test Condition, Idle Mode CC Reset = Vss after a high pulse during at least 24 clock cycles V CC (NC) CLOCK SIGNAL Figure 41. I Test Condition, Power-Down Mode CC Reset = Vss after a ...
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DC Parameters for A/D Converter AC Parameters Explanation of the AC Symbols AT89/83EB5114 0°C to +70° -40°C to +85° ...
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External Clock Drive Characteristics (XTAL1) External Clock Drive Waveforms A/D Converter 4311C–8051–02/08 Table 4. Max frequency for Derating Formula Regarding the Speed Grade Freq (MHz) T (ns) 1. Oscillator speed is limited to 24 Mhz Symbol Parameter T Oscillator Period ...
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PWM Outputs AC Testing Input/Output Waveforms VCC-0.5 V INPUT/OUTPUT Float Waveforms Clock Waveforms AT89/83EB5114 90 Symbol Parameter Tr Rise time of PWM outputs Tf Fall time of PWM outputs Figure 44. AC Testing Input/Output Waveforms 0.2VCC+0.9 0.2VCC-0.1 0. ...
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Figure 46. Clock Waveforms STATE4 INTERNAL CLOCK P1P2 XTAL2 PORT OPERATION MOV DEST PORT (P1, P3, P4) (INCLUDES INT0, INT1, TO, T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0) 4311C–8051–02/08 STATE1 STATE2 STATE5 STATE6 P1P2 P1P2 P1P2 P1P2 OLD DATA ...
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Typical Application Figure 47. Typical Application Diagram VCC VSS NC PFC measurement DC voltage Lamp detection Analog I/O Lamp current Vref NC NC AT89/83EB5114 92 VCC P3.0/W0M0 P3.1/W0M1 RST P3.2/INT0 P3.3/W0M2/AIN4 P4.0/AIN0 P3.4/T0/AIN5 P4.1/AIN1 P3.5/W1M0 P4.2/AIN2 P3.6 P4.3/AIN3 EE P3.7 ...
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... Ordering Information Table 5. Possible Order Entries Memory Part Number AT83EB5114xxxTGRIL AT89EB5114-TGSIL 4Kb ROM AT83EB5114xxxTGRUL 4Kb Flash AT89EB5114-TGSUL 4311C–8051–02/08 Supply Temperature Size Voltage Range 3 to 3.6V Industrial & Green 3 to 3.6V Industrial & Green Max Frequency Package OBSOLETE 40 MHz S020 40 MHz SO20 ...
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Package Drawings SO20 Document Revision History Changes from 4311B to 4311C AT89/83EB5114 94 1. Removed non-green part numbers from Ordering Information. 4311C–8051–02/08 ...
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