AT86RF230 Atmel Corporation, AT86RF230 Datasheet
AT86RF230
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AT86RF230 Summary of contents
Page 1
... I/O and Packages: - 32-pin Low-Profile QFN - RoHS/Fully Green • Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-66, RSS-210 • Compliant to IEEE 802.15.4-2003 5131E-MCU Wireless-02/09 AT86RF230 Low Power 2.4 GHz Transceiver for ZigBee, IEEE 802.15.4, 6LoWPAN, RF4CE and ISM Applications AT86RF230 5131E-MCU Wireless-02/09 1 ...
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... Industrial control, sensing and automation (SP100, WirelessHART) • Home and building automation • Consumer electronics • PC peripherals The AT86RF230 can be operated by using an external microcontroller like ATMEL’s AVR microcontrollers. A comprehensive software programming description can be found in the application note AVR2009 “AT86RF230 – Software Programming Model”. 24 ...
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... The number of external components is minimized such that only an antenna, a crystal and four decoupling capacitors are required. The bidirectional differential antenna pins are used for transmission and reception, so that no external antenna switch is needed. The AT86RF230 block diagram is shown in Figure 3-1. Analog Domain TX power XOSC ...
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... External supply voltage; analog domain Supply Regulated 1.8V supply voltage; analog domain Ground Analog ground Ground Analog ground Ground Analog ground Ground Analog ground; Exposed Paddle of QFN package EVDD, DEVDD EVDD and DEVDD are analog and digital supply voltage pins of the AT86RF230 radio transceiver. 5131E-MCU Wireless-02/09 ...
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... AVSS and DVSS are analog and digital ground pins respectively. The analog and digital power domains should be separated on the PCB, for further details see application note AVR2005 "Design Considerations for the AT86RF230". RFP, RFN A differential RF port (RFP/RFN) provides common-mode rejection to suppress the switching noise of the internal digital signal processing blocks ...
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... Parasitic capacitance (CPAR) of the pins must be considered as additional load capacitance to the crystal. The digital interface of the AT86RF230 compromises pins SEL , SCLK, MOSI and MISO forming the serial peripheral interface (SPI) and pins CLKM, IRQ, SLP_TR and RST used as additional control signal between radio transceiver and microcontroller. ...
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... Register Bit Value (1) PAD_IO Notes: 1. Reset values of register bits are underlined characterized in the document. • Bit [5:6] – PAD_IO_CLKM The register bits PAD_IO_CLKM set the output driver current of pin CLKM. AT86RF230 H ≙ pull-up, L ≙ pull-down PAD_IO_CLKM R/W ...
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... Refer to section 9.6.5. • Bit [2:0] – CLKM_CTRL Refer to section 9.6.5. An application circuit of the AT86RF230 radio transceiver with a single-ended RF connector is shown in Figure 5-1. The balun B1 transforms the 100Ω differential RF port (RFP/RFN 50Ω single-ended RF port. The capacitors C1 and C2 provide AC coupling of the RF signals to the RF pins. ...
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... Capacitors CB1 and CB3 are bypass capacitors for the integrated analog and digital voltage regulators to ensure stable operation (1 µF recommended value). All decoupling and bypass capacitors should be placed as close as possible to the AT86RF230 pins and should have a low-resistance and low-inductance connection to ground to achieve the best performance ...
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... GPIO4 Microcontrollers with a master SPI, such as Atmel’s AVR family, interface directly to the AT86RF230. The SPI is used for Frame Buffer and register access. The additional control signals are connected to the GPIO/IRQ interface of the microcontroller. Table 6-1 introduces the radio transceiver I/O signals and their functionality. ...
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... SEL = L enables the MISO output driver of the radio transceiver. The MSB of MISO is valid after t (see section 11.4 parameter 11.4.3) and is updated at each falling edge of 1 SCLK. If the MISO output driver is disabled, there is no internal pull-up resistor connected to the output. Driving the appropriate signal level must be ensured by the AT86RF230 , and ...
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... Register Access Mode AT86RF230 12 master device or an external pull-up resistor. Note, when both SEL and RST are active, the MISO output driver is also enabled. The MOSI line is sampled by the radio transceiver at the rising edge of SCLK. The signal must be stable before and after the rising edge of SCLK as specified by t refer to section 11.4 parameters 11.4.5 and 11.4.6. This mode of SPI operation is commonly called “ ...
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... Figure 6-8 illustrates the packet structure of a Frame Buffer read access. Note, the Frame Buffer read access can be terminated at any time without any consequences by setting SEL = H, e.g. after reading the frame length byte only. AT86RF230 byte 2 (data byte) XX read data[7:0] ...
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... Figure 6-10. Example SPI Sequence - Frame Buffer Read Sequence of a Frame with 4-byte PSDU SEL SCLK MOSI COMMAND MISO XX 6.2.3 SRAM Access Mode AT86RF230 14 The number of bytes n for one Frame Buffer access is calculated as follow: Receive frame_length [command byte, frame length byte, PSDU data, LQI byte] Transmit frame_length [command byte, frame length byte, PSDU data] The maximum value of frame_length is 127 bytes. That means that n ≤ ...
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... Frame Buffer until the SRAM access is terminated by setting SEL = H. Figure 6-13 and Figure 6-14 illustrate an example SPI sequence of a SRAM access to write and read a data package of 5 byte length respectively. DATA 1 DATA AT86RF230 DATA 3 DATA 4 DATA ...
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... Frame Buffer access violations are not indicated by a TXR_UR interrupt when using the SRAM access mode (see section 9.3.3) The AT86RF230 can be identified by four registers. One register contains an unique part number and one register the corresponding version number. Additional two registers contain the JEDEC manufacturer ID. ...
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... Table 6-6. JEDEC Manufacturer ID – Bits [15:8] Register Bits Value[7:0] MAN_ID_1 0x00 The SLP_TR signal is a multi-functional pin. Its function relates to the current state of the AT86RF230 and is summarized in Table 6-7. The radio transceiver states are explained in detail in section 7. AT86RF230 Description AT86RF230 Revision A AT86RF230 Revision B ...
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... AT86RF230 awakes when the microcontroller releases pin SLP_TR. This concept provides the lowest possible power consumption. For synchronous systems, where CLKM is used as a microcontroller clock source and the SPI master clock (SCLK) is directly derived from CLKM, the AT86RF230 supports an additional power-down mode for receive operating states RX_ON and RX_AACK_ON. ...
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... RX_ON_NOCLK/RX_AACK_ON_NOCLK and state RX_ON, because only the CLKM output is switched off. The AT86RF230 differentiates between six interrupt events. Each interrupt is enabled or disabled by writing the corresponding bit to the interrupt mask register 0x0E (IRQ_MASK). Internally, each interrupt is stored as a separate bit of the interrupt status register. All interrupt lines are combined via logical “ ...
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... Register Description AT86RF230 20 Register 0x0E (IRQ_MASK) The IRQ_MASK register is used to enable (set register bit disable (set register bit to 0) interrupt events by writing the corresponding bit to the interrupt mask register. Bit 7 0x0E MASK_BAT_LOW MASK_TRX_UR Read/Write R/W R/W Reset value 1 Bit 3 0x0E MASK_TRX_END MASK_RX_START MASK_PLL_UNLOCK MASK_PLL_LOCK ...
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... Figure 7-1. Basic Operating Mode State Diagram (for State Transition Timing Data Refer to Table 7-1) 7.1.1 State Control 5131E-MCU Wireless-02/09 This section summarizes all states to provide the basic functionality of the AT86RF230, such as receiving and transmitting frames, and powering up and down. The Basic Operating Mode is designed for IEEE 802.15.4 applications; the corresponding radio transceiver states are shown in Figure 7-1 ...
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... TRX_OFF. In SLEEP state, the entire radio transceiver is disabled. No circuitry is operating. The AT86RF230 current consumption is reduced to leakage current only. This state can only be entered from state TRX_OFF by setting the pin SLP_TR = H. If CLKM is enabled, the SLEEP state is entered 35 CLKM cycles after the rising edge. At that time CLKM is turned off ...
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... AT86RF230 using the state RX_ON_NOCLK. This state can only be entered by setting SLP_TR = H while the AT86RF230 is in the RX_ON state. The CLKM pin is disabled 35 clock cycles after the rising edge at the SLP_TR pin. This allows the microcontroller to complete its power-down sequence. The ...
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... TRX_END interrupt and returns to PLL_ON state. Note that in case the PHR indicates a frame length of zero, the transmission is aborted. All interrupts of the AT86RF230 (see Table 6-8) are supported during operation in Basic Operating Mode. Two interrupts are used to support RX and TX operation of the radio transceiver. On receive the RX_START interrupt indicates the detection of a valid SFD ...
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... Clock stable TRX_OFF 16 DVREG FTN BG AVREG μ s PLL_ON, RX_ON Typical block settling time, stays on Block active waiting for SPI commands AT86RF230 time [µs] PLL_ON TRX_END RX_LISTEN TRX_END 16 µs 1100 Time [μs] IRQ PLL locked PLL_ON RX_ON Time [μs] PLL RX_ON ...
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... TR3 4 t TRX_OFF → TR4 AT86RF230 26 In TRX_OFF state, entering the commands PLL_ON or RX_ON initiates a ramp-up sequence of the analog voltage regulator. RX_ON state can be entered any time during PLL_ON state regardless whether the PLL has already locked. When the wake-up sequence is started from P_ON state (V transceiver) the state machine stops after the 128 µ ...
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... CCA measurement. Note, a read access to the register clears bits CCA_DONE and CCA_STATUS. This register is used for Extended and Basic Operating Mode. The Extended Operating Mode functionality is described in section 7.2. Bit 7 0x01 CCA_DONE CCA_STATUS Read/Write R Reset value 0 AT86RF230 Reserved TRX_STATUS TRX_STATUS ...
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... AT86RF230 28 Bit 3 0x01 R Read/Write Reset value 0 • Bit 7 – CCA_DONE Refer to section 8.6. • Bit 6 – CCA_STATUS Refer to section 8.6. • Bit 5 – Reserved • Bit [4:0] – TRX_STATUS The register bits TRX_STATUS signal the current radio transceiver status. If the requested state transition is not completed yet, the TRX_STATUS returns STATE_TRANSITION_IN_PROGRESS ...
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... MAC implementation including reduced code size, the possible use of a smaller microcontroller or the ability to simplify the handling of time-critical tasks. The Extended Operating Mode is designed to support IEEE 802.15.4-2003 standard compliant frames. While using the Extended Operating Mode, the AT86RF230 radio transceiver supports: • Automatic address filtering • ...
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... Interrupt and transaction return code generation For details on TX_ARET transaction see section 7.2.3.2. The AT86RF230 state diagram including the Extended Operating Mode states is shown in Figure 7-5. Yellow marked states represent the Basic Operating Mode, blue marked states represent the Extended Operating Mode. ...
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... PLL_ON as described by the state diagram in Figure 7-5. The completion of each requested state change shall always be confirmed by reading the register 0x01 (TRX_STATUS). 3 (from all states) RST=L RST=H RESET 4 Frame 11 End BUSY_TX (Transmit State) 10 TX_START or SLP_TR=H From TRX_OFF TX_START or SLP_TR=H BUSY_TX_ARET Frame End AT86RF230 31 ...
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... IEEE 802.15.4-2003 section 7.5.1.3), and the CSMA_SEED_0 and CSMA_SEED_1 register bits (registers 0x2D, 0x2E) define a random seed for the back-off-time random- number generator in the AT86RF230. The register bits MAX_CSMA_RETRIES (register 0x2C) configures how often the radio transceiver retries the CSMA-CA algorithm after a busy channel is detected ...
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... TRAC_STATUS are set to SUCCESS after the reception of the frame was completed. The microcontroller can then upload the frame. The AT86RF230 detects whether an ACK frame needs to be sent. In that case, the radio transceiver automatically generates an ACK frame which is transmitted 12 symbol periods after the end of the received frame ...
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... Figure 7-7. Example Timing of an RX_AACK Transaction 0 64 Frame Type TRX_STATE RX_AACK_ON RX/TX IRQ Typ. Processing Delay AT86RF230 34 Figure 7-6. Flow Diagram of RX_AACK 512 Data Frame (Length = 10, ACK=1) SFD BUSY_RX_AACK RX TRX_END μ 192 s (12 symbols) 704 1088 ACK Frame RX_AACK_ON TX μ μ time [ s] ...
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... IEEE 802.15.4-2003 section 7.5.1. clear channel is detected during CSMA-CA execution, the radio transceiver proceeds to transmit the frame. During frame transmission the AT86RF230 parses the frame control field of the downloaded frame to check if an ACK reply is expected ACK is expected, the radio transceiver switches into receive mode to wait for valid ACK reply. An ACK is considered as valid if its FCS is correct, and if the sequence number of the ACK matches the sequence number of the previously transmitted frame ...
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... AT86RF230 36 Figure 7-8 Flow Diagram of TX_ARET Figure 7-9 shows a TX_ARET transaction with the related timing. In this example a data frame of length 10 with ACK request is transmitted. Furthermore the following constrains are assumed: • Register bits MIN_BE (register 0x2E) are set not delay the execution of the CCA algorithm after the rising edge at pin SLP_TR • ...
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... If the AT86RF230 is listening for an incoming frame and the microcontroller is not running an application, the microcontroller can be powered down to decrease the total system power consumption. This special power-down scenario for systems running in clock synchronous mode (see section 6.4) is supported by the AT86RF230 using the state RX_AACK_ON_NOCLK ...
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... AVR2009 “AT86RF230 – Software Programming Model”). IRQ_0: PLL_LOCK Disabled for regular operation. In case of occurrence, the device status needs to be examined (refer to AVR2009 “AT86RF230 – Software Programming Model”). Description Radio transceiver status, CCA result State control ...
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... A successful state transition shall be confirmed by reading register bits TRX_STATUS in register 0x01 (TRX_STATUS). Bit 7 0x02 TRAC_STATUS Read/Write R Reset value 0 Bit 3 0x02 Read/Write R/W R/W Reset value 0 AT86RF230 State Description P_ON BUSY_RX BUSY_TX RX_ON TRX_OFF (Clock State) PLL_ON (TX_ON) SLEEP BUSY_RX_AACK BUSY_TX_ARET RX_AACK_ON TX_ARET_ON RX_ON_NOCLK RX_AACK_ON_NOCLK BUSY_RX_AACK_NOCLK STATE_TRANSITION_IN_PROGRESS All other values are reserved ...
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... AT86RF230 40 • Bit [7:5] – TRAC_STATUS The status of the TX_ARET algorithm is indicated by register bits TRAC_STATUS. Details of the algorithm and a description of the status information are given in section 7.2.3.2. Table 7-8. State Control Register, Register Bits TRAC_STATUS TX_ARET Register Bits Value[7:5] TRAC_STATUS • Bit [4:0] – TRX_CMD A write access to register bits TRX_CMD initiates a radio transceiver state transition towards the new state ...
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... MAX_CSMA_RETRIES specifies the maximum number of retries in TX_ARET transaction to repeat the random back-off/CCA procedure before the transaction gets cancelled. Even though the valid range of MAX_CSMA_RETRIES is [0, 1 … 5] according to IEEE 802.15.4-2003, the AT86RF230 can be configured maximum value of 7 retries. • Bit 0 – Reserved ...
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... Register Description – Address Registers AT86RF230 42 acknowledgment frame is set in response to a MAC command data request frame, otherwise not. The register bit has to be set before finishing the SHR transmission of the acknowledgment frame. This is 352 µs (192 µs ACK wait time + 160 µs SHR transmission) after the TRX_END interrupt issued by the frame to be acknowledged. • ...
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... This register contains bits [39:32] of the 64 bit IEEE address for address filtering. Bit 0x28 Read/Write R/W R/W R/W Reset value Register 0x29 (IEEE_ADDR_5) This register contains bits [47:40] of the 64 bit IEEE address for address filtering. Bit 0x29 Read/Write R/W R/W R/W Reset value AT86RF230 IEEE_ADDR_0 R/W R/W R/W R/W R IEEE_ADDR_1 R/W R/W R/W R/W R ...
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... AT86RF230 44 Register 0x2A (IEEE_ADDR_6) This register contains bits [55:48] of the 64 bit IEEE address for address filtering. Bit 0x2A Read/Write R/W R/W R/W Reset value Register 0x2B (IEEE_ADDR_7) This register contains bits [63:56] of the 64 bit IEEE address for address filtering. Bit 0x2B Read/Write R/W R/W R/W Reset value ...
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... The SHR consists of a four-octet preamble field (all zero), followed by a single SFD octet which has the predefined value 0xA7. When transmitting, the SHR is automatically generated by the AT86RF230, and prefixed to the frame that has been read from the Frame Buffer. The transmission of the SHR requires 160 µs (10 symbols). This allows the microcontroller to initiate a transmission and to start downloading the frame contents subsequently ...
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... It indicates that the transmitter of the acknowledgement frame has more data to send for the recipient of the acknowledgement frame. For acknowledgment frames automatically generated by the AT86RF230, this bit is set according to the content of register bit AACK_SET_PD in register 0x2E (CSMA_SEED_1). Bit 5 forms the “acknowledgment request” subfield. If this bit is set within a data or MAC command frame that is not broadcast, the recipient shall acknowledge the reception of the frame within the time specified by IEEE 802.15.4-2003 (i.e. within 192 µ ...
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... The address filter in the AT86RF230 has been designed to apply to IEEE 802.15.4-2003 compliant frames only. This is the actual MAC payload usually structured according to the individual frame type descriptions in IEEE 802 ...
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... MSDU fields). The frame check sequence has a length of 16 bit and is located in the last two bytes of a frame (MAC footer, see Figure 8-2). The AT86RF230 applies an FCS check on each received frame. The FCS check result is stored to register bit RX_CRC_VALID in register 0x06 (PHY_RSSI). On transmit the radio transceiver can be configured to autonomously compute and append the FCS bytes ...
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... Automatic FCS check 8.2.5 Register Description 5131E-MCU Wireless-02/09 The AT86RF230 automatic FCS generation and insertion is enabled by setting register bit TX_AUTO_CRC_ON to 1. For a frame with a frame length field (PHR) specified ≤ N ≤ 127), the FCS is calculated on the first N -2 PSDU octets in the Frame Buffer, and the resulting 16 bit FCS field is appended during transmission ...
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... IEEE 802.15.4-2003 channel. No attempt is made to identify or decode signals on the channel. The ED value is calculated by averaging RSSI values over eight symbols (128 µs). There are two ways implemented in the AT86RF230 to initiate an ED measurement: • Manually write access to register 0x07 (PHY_ED_LEVEL), or • Automatically, by detecting a valid SFD of an incoming frame. ...
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... Wireless-02/09 The measurement result is stored to register 0x07 (PHY_ED_LEVEL) 140 µs after its initialization. The value is always 0 if the AT86RF230 is not in any of the RX states. Thus by using Basic Operating Mode, a valid ED value from the currently received frame is accessible 140 µs after the RX_START interrupt and remains valid until a new RX_START interrupt is generated by the next incoming frame or until another ED measurement is initiated manually ...
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... Overview 8.4.2 Reading RSSI 8.4.3 Data Interpretation 8.4.4 Register Description AT86RF230 52 The RSSI is a 5-bit value indicating the receive power in the selected channel, in steps of 3 dB. No attempt is made to distinguish between IEEE 802.15.4 signal and other signal source, only the received signal power is evaluated. The RSSI provides the basis for ED measurement ...
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... LQI values in between should be uniformly distributed between these two limits. The AT86RF230 determines the link quality of a radio link. The radio transceiver uses correlation results of multiple symbols within a frame to determine the LQI value. This is done for each received frame ...
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... Data Interpretation 8.6 Clear Channel Assessment (CCA) 8.6.1 Overview AT86RF230 54 information can be read as an extra byte from the Frame Buffer (see section 9.1). The LQI byte can be uploaded after the TRX_END interrupt. A low LQI value is associated with low signal strength and/or high signal distortions. ...
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... RSSI_BASE_VAL+2•CCA_ED_THRES [dBm]. Using the Basic Operating Mode, a CCA request can be initiated manually by setting CCA_REQUEST = 1 in register 0x08 (PHY_CC_CCA), if the AT86RF230 is in any RX state. The CCA computation is done over eight symbol periodes and the result is accessible 140 µs after the request. ...
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... AT86RF230 56 Table 8-5. Status CCA Algorithm Register Bit Value CCA_DONE 0 1 • Bit 6 – CCA_STATUS CCA_STATUS register bit indicates the result of a CCA request. Each read access to register 0x01 resets the CCA_STATUS bit. Table 8-6. Status CCA Result Register Bit Value CCA_STATUS 0 1 • Bit 5 – Reserved • ...
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... R/W R/W Read/Write Reset value 0 • Bit [7:4] – Reserved • Bit [3:0] – CCA_ED_THRES The register bits CCA_ED_THRES define the threshold value of the CCA-ED measurement. A cannel is indicated as busy when the received signal power is above RSSI_BASE_VAL + 2 • CCA_ED_THRES [dBm]. AT86RF230 Reserved R/W R ...
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... Transmitter (TX) 9.2.1 Overview AT86RF230 58 The AT86RF230 receiver is spitted into an analog radio front end and a digital base band processor (RX BBP), see Figure 3-1. The RF signal is amplified by a low noise amplifier (LNA) and converted down to an intermediate frequency by a mixer. Channel selectivity is performed using an integrated band pass filter ...
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... Reset value 0 • Bit 7 – TX_AUTO_CRC_ON Refer to sections 7.2.6 and 8.2. • Bit [6:4] – Reserved • Bit [3:0] – TX_PWR The register bits TX_PWR sets the TX output power of the AT86RF230. The available power settings are summarized in Table 9-1. Table 9-1. PA Output Power Setting Register Bits Value [3:0] TX_PWR ...
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... The AT86RF230 contains a 128 byte dual port SRAM. One port is connected to the SPI interface, the other to the internal TX/RX BBP port. For data communication both ports are independent and simultaneously accessible. Access conflicts are indicated by a TRX under run (TRX_UR) interrupt. ...
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... FCS field when using the automatic FCS generation. For non IEEE 802.15.4-2003 frames, the minimum PSDU length supported by the AT86RF230 is one byte. Access conflicts may occur when reading or writing data simultaneously at the two independent ports of the Frame Buffer, BBP and SPI. Both of these ports have its own address counter that points to the Frame Buffer’ ...
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... Low dropout (LDO) voltage regulator • Configurable for usage of external voltage regulator The internal voltage regulators supply the low voltage domains of the AT86RF230. The AVREG provides the regulated 1.8V supply voltage for the analog section and the DVREG supplies the 1.8V supply voltage for the digital section. A simplified schematic of the internal voltage regulator is shown in Figure 9-2 ...
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... Bit 6 – AVDD_OK This register bit AVDD_OK indicates if the internal 1.8V regulated supply voltage AVDD has settled. The bit is set to logic high, if AVREG_EXT = 1. Table 9-3 Regulated Voltage Supply Control for Analog Building Blocks Register Bit Value AVDD_OK 0 1 AT86RF230 Reserved R R/W R ...
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... Battery Monitor (BATMON) 9.5.1 Overview AT86RF230 64 • Bit [5:4] – Reserved • Bit 7 – DVREG_EXT The register bit DVREG_EXT defines whether the internal digital voltage regulator or an external regulator is used to supply the digital low voltage building blocks of the radio transceiver. Table 9-4. Regulated Voltage Supply Control for Digital Building Blocks ...
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... R Reset value 0 Bit 3 0x11 Read/Write R/W R/W Reset value 0 • Bit [7:6] – Reserved • Bit 5 – BATMON_OK The register bit BATMON_OK indicates the level of the external supply voltage with respect to the programmed threshold BATMON_VTH. AT86RF230 BATMON_OK BATMON_HR BATMON_VTH ...
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... Crystal Oscillator (XOSC) AT86RF230 66 Table 9-6. Battery Monitor Status Register Bit Value BATMON_OK 0 1 • Bit 4 – BATMON_HR The register bit BATMON_HR selects the range and resolution of the battery monitor. Table 9-7. Battery Monitor Voltage Range Settings Register Bit Value BATMON_HR 0 1 • Bit [3:0] – BATMON_VTH The threshold value for the battery monitor is set with register bits BATMON_VTH ...
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... Overview 9.6.2 Integrated Oscillator Setup 5131E-MCU Wireless-02/09 The crystal oscillator generates the reference frequency for the AT86RF230. All other internally generated frequencies of the radio transceiver are derived from this unique frequency. Therefore, the overall system performance is mainly based on the accuracy of this reference frequency. The external components of the crystal oscillator should be selected carefully and the related board layout should be done meticulously (refer to section 5) ...
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... CLKM_SHA_SEL = 0, changing the register bits CLKM_CTRL (register 0x03, TRX_CTRL_0) immediately (CLKM_SHA_SEL = 1) the new clock rate is supplied when leaving the SLEEP state the next time. XTAL_TRIM[3:0] C TRIM AT86RF230 PCB XTAL1 16MHz CX C PAR AT86RF230 XTAL1 PCB 16 MHz affects the CLKM clock rate. Otherwise 5131E-MCU Wireless-02/09 ...
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... PAD_IO_CLKM • Bit 3 – CLKM_SHA_SEL The register bit CLKM_SHA_SEL defines the commencement of the CLKM clock rate modifications when changing register bits CLKM_CTRL. Table 9-10. Commencement of CLKM Clock Rate Modification Register Bit Value CLKM_SHA_SEL 0 AT86RF230 PAD_IO_CLKM R/W R CLKM_CTRL ...
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... AT86RF230 70 Register Bit Value 1 • Bit [2:0] – CLKM_CTRL The register bits CLKM_CTRL set clock rate of pin CLKM. Table 9-11. Clock Rate at Pin CLKM Register Bit Value CLKM_CTRL Register 0x12 (XOSC_CTRL) The register XOSC_CTRL controls the operation of the crystal oscillator. ...
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... Fully integrated fractional-N synthesizer • Autonomous calibration loops for stable operation within the operating range • Two PLL-interrupts for status indication The synthesizer of the AT86RF230 is implemented as a fractional-N PLL. The PLL is fully integrated and configurable by registers 0x08 (PHY_CC_CCA), 0x1A (PLL_CF) and 0x1B (PLL_DCU). ...
Page 72
... PLL Interrupt Handling 9.7.5 Register Description AT86RF230 72 (PLL_DCU). To start the calibrations routines the device should be in state PLL_ON. The center frequency tuning takes a maximum of 80 µs. The completion is indicated by a PLL_LOCK interrupt. The delay cell calibration loop is completed after 6 µs. This is typically not indicated by a PLL_LOCK interrupt. ...
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... Bit [6:0] – Reserved Register 0x1B (PLL_DCU) The register PLL_DCU controls the operation of the delay cell calibration loop. Bit 7 0x1B PLL_DCU_START Read/Write R/W Reset value 0 Bit 3 0x1B Read/Write R/W R/W Reset value 0 AT86RF230 Channel Number Center Frequency [MHz Reserved ...
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... The register bit is cleared immediately after the register write operation. • Bit [6:0] – Reserved The filter-tuning unit is a separate block within the AT86RF230. The filter-tuning result is used to provide a correct SSBF transfer function and PLL loop-filter time constant independent of temperature effects and part-to-part variations. ...
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... Frame Transmit Procedure 5131E-MCU Wireless-02/09 This section describes basic procedures to receive and transmit frames using the AT86RF230. For a detailed programming description refer to application note AVR2009 “AT86RF230 – Software Programming Model”. While in state RX_ON the radio transceiver searches for incoming frames on the selected channel ...
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... AT86RF230 76 Figure 9-7. Frame Transmit Procedure - Transactions between AT86RF230 and Microcontroller Alternatively, the frame transmission can be started before the frame data download as described in Figure 9-8. This is useful for time critical applications. At the rising edge of SPL_TR, the radio transceiver starts transmitting the preamble and the SFD field, which takes about 176 µ ...
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... DD V 1.65 1.8 DD1.8 Test Conditions (unless otherwise stated 25°C op Symbol Min Typ V V – 0 – 0 AT86RF230 Max Unit Conditions/Notes 150 °C 260 °C kV Compl. to [2] V Compl. to [3] +14 dBm V +0.3 DD 2.0 Max Unit Conditions/Notes +85 °C 3.6 V 1.95 V When using external voltage regulators (see section 9 ...
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... Table 11-5. General RF Parameters No Parameter 11.5.1 Frequency range 11.5.2 Bit rate 11.5.3 Chip rate 11.5.4 Reference oscillator frequency 11.5.5 Reference oscillator settling time Reference frequency accuracy 11.5.6 for proper functionality 11.5.7 TX signal 20 dB bandwidth AT86RF230 78 Test Conditions (unless otherwise stated 3V 25° Symbol Min Typ ...
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... Test Conditions (unless otherwise stated 3V 2.45 GHz 25°C, Measurement setup see Figure 5 Symbol Min Typ -101 -75 AT86RF230 Max Unit Conditions/Notes 6 dBm Maximum configurable value dB Configurable in register PHY_TX_PWR ± %rms dBm dBm Complies with -36 dBm ...
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... Supply current TRX_OFF state 11.8.4 Supply current SLEEP state 11.8.5 Supply current PLL_ON state 11.9 Crystal Parameter Requirements Table 11-9. Crystal Parameter Requirements No Parameter 11.9.1 Crystal frequency 11.9.2 Load capacitance 11.9.3 Static capacitance 11.9.4 Series resistance AT86RF230 80 Symbol Min Typ -300 IIP3 -9 IIP2 - Test Conditions (unless otherwise stated 3V 2.45 GHz 25° ...
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... CSMA_SEED_1 MIN_BE 5131E-MCU Wireless-02/09 The AT86RF230 provides a register space of 64 8-bit registers, which is used to configure, control and monitor the radio transceiver. The registers can be accessed in any order. Note: All registers not mentioned within the following table are reserved for internal use and must not be overwritten ...
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... AT86RF230 82 Notes: • Reset values in Table 12-2 are only valid after a power on reset. After a reset procedure ( RST = L) as described in section 7.1.4.2 the reset values of selected registers (e.g. registers 0x01, 0x10, 0x11) can differ from that in Table 12-2. • Read value of register 0x30 after a reset in state: ...
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... Medium access control MFR — MAC Footer MHR — MAC header MSB — Most significant bit MSDU — MAC service data unit MSK — Minimum shift keying NOP — No operation O-QPSK — Offset-quadrature phase shift keying PA — Power amplifier AT86RF230 83 ...
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... AT86RF230 84 PAN — Personal area network PCB — Printed circuit board PER — Packet error rate PHY — Physical layer PHR — PHY Header PLL — Phase-locked loop POR — Power-on reset PPF — Poly-phase filter PRBS — Pseudo random binary sequence PSDU — ...
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... Temperature Range 1.8V – 3.6V Industrial (-40° +85° C) Lead-free/Halogen-free T&R quantity 5,000. Note: Please contact your local Atmel sales office for more detailed ordering information and minimum quantities. Recommended soldering profile is specified in IPC/JEDEC J-STD-.020C. Velocity [m/ 2.5 AT86RF230 Thermal Resistance Theta ja [K/W] 40.9 35.7 32.0 85 ...
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... Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. Package Drawing Contact: packagedrawings@atmel.com AT86RF230 86 D Pin 1 Corner Pin 1 Corner ...
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... The Continuous Transmission Test Mode offers the following features: • Continuous frame transmission • Continuous wave signal transmission The AT86RF230 offers a Continuous Transmission Test Mode to support final application/production tests as well as certification tests. Using this test mode the radio transceiver transmits continuously a previously downloaded frame data (PRBS mode continuous wave signal (CW mode) ...
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... L) RESET 17 The functionality of the Continuous Transmit Mode is not characterized by Atmel and therefore not guaranteed. The normal operation of the AT86RF230 is only guaranteed if pin TST is always logic low. Write 0x01 to register 0x0E Write 0x03 to register 0x02 Write 0x10 to register 0x03 Write 0x33 to register 0x08 ...
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... Appendix B - Errata AT86RF230 Rev. B AT86RF230 Rev. A 5131E-MCU Wireless-02/09 No known errata. 1. Data frames with destination address=0xFFFF is acknowledged in RX_AACK According to IEEE 802.15.4-2003 data frames with destination address=0xFFFF (broadcast) should not have the acknowledgment request subfield set in the frame control field. If such a non-standard compliant data frame arrives, a device in RX_AACK state acknowledges that frame ...
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... SFD. One cause of continuous wave interferers may be due to crosstalk from clock. Fix/Workaround For further details see application note AVR2005 "Design Considerations for the AT86RF230". 5. TRX_END_IRQ occurs sometimes too late in TX_ARET_ON state This behavior can be observed, if the procedure TX_ARET performs frame retransmissions. ...
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... Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs) [2] ANSI / ESD-STM5.1-2001: ESD Association Standard Test Method for electrostatic discharge sensitivity testing – Human Body Model (HBM) [3] ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic discharge sensitivity testing – Charged Device Model (CDM) AT86RF230 91 ...
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... Updated parameter 11.4.4 3. Minor editorial changes The AT86RF230 data sheet was fully revised and modifications of silicon revision AT86RF230 Rev. B were incorporated. A migration note of silicon revision A to revision B is available on www.atmel.com. The most important modifications are: 4. Device version number in register 0x1D (VERSION_NUM) changed to 2 (section 6.3) 5 ...
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... Register Description .................................................................................................... 27 7.2 Extended Operating Mode ................................................................................... 29 7.2.1 State Control ............................................................................................................... 31 7.2.2 Configuration ............................................................................................................... 32 7.2.3 Extended Operating Mode Description........................................................................ 33 7.2.4 Interrupt Handling in Extended Operating Mode ......................................................... 37 7.2.5 Register Summary....................................................................................................... 38 7.2.6 Register Description – Control Registers..................................................................... 38 7.2.7 Register Description – Address Registers ................................................................... 42 8 Functional Description .....................................................................45 8.1 Introduction - Frame Format................................................................................. 45 8.1.1 PHY Protocol Layer Data Unit (PPDU)........................................................................ 45 AT86RF230 93 ...
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... AT86RF230 94 8.1.2 MAC Protocol Layer Data Unit (MPDU)....................................................................... 46 8.2 Frame Check Sequence (FCS) ............................................................................ 48 8.2.2 CRC calculation........................................................................................................... 48 8.2.3 Automatic FCS generation .......................................................................................... 49 8.2.4 Automatic FCS check .................................................................................................. 49 8.2.5 Register Description .................................................................................................... 49 8.3 Energy Detection (ED) ......................................................................................... 50 8.3.1 Overview ..................................................................................................................... 50 8.3.2 Request an ED Measurement ..................................................................................... 50 8.3.3 Data Interpretation....................................................................................................... 51 8.3.4 Register Description .................................................................................................... 51 8.4 Received Signal Strength Indicator (RSSI) .......................................................... 51 8.4.1 Overview ..................................................................................................................... 52 8.4.2 Reading RSSI.............................................................................................................. 52 8.4.3 Data Interpretation....................................................................................................... 52 8 ...
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... Current Consumption Specifications.................................................................. 80 11.9 Crystal Parameter Requirements ....................................................................... 80 12 Register Reference .........................................................................81 Abbreviations .......................................................................................83 13 Ordering Information ......................................................................85 14 Soldering Information.....................................................................85 15 Package Thermal Properties..........................................................85 16 Package Drawing – 32QN1 .............................................................86 Appendix A - Continuous Transmission Test Mode .........................87 A.1 - Overview ............................................................................................................ 87 A.2 - Configuration...................................................................................................... 87 A.3 - Disclaimer .......................................................................................................... 88 Appendix B - Errata .............................................................................89 AT86RF230 Rev. B .................................................................................................... 89 AT86RF230 Rev. A .................................................................................................... 89 References............................................................................................91 AT86RF230 95 ...
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... AT86RF230 96 Data Sheet Revision History ...............................................................92 Rev. 5131D-ZIGB-12/03/07........................................................................................ 92 Rev. 5131C-ZIGB-05/22/07........................................................................................ 92 Rev. 5131A-ZIGB-06/14/06........................................................................................ 92 Table of Contents.................................................................................93 5131E-MCU Wireless-02/09 ...
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... Wireless-02/09 AT86RF230 97 ...
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... Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2009 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, AVR® and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. AT86RF230 Atmel Europe Atmel Japan Le Krebs 9F, Tonetsu Shinkawa Bldg ...