AT86RF232 Atmel Corporation, AT86RF232 Datasheet - Page 119

• Manufacturer Part Number: AT86RF232
• Manufacturer: Atmel Corporation

Specifications of AT86RF232

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -100
• Receive Current Consumption (ma): 11.8
• Transmit Current Consumption (ma): 13.8
• Link Budget (dbm): 103

9.7.5 Interrupt Handling
9.7.6 Register Description
8321A–MCU Wireless–10/11
Bit
0x08
Read/Write
Reset value
Bit
0x08
Read/Write
Reset value
If the Atmel AT86RF232 PLL operates for a long time on the same channel, for
example more than five minutes, or the operating temperature changes significantly, it
is recommended to initiate the calibration loops manually.
Both calibration loops can be initiated manually by setting PLL_CF_START = 1
(register 0x1A, PLL_CF) and register bit PLL_DCU_START = 1 (register 0x1B,
PLL_DCU). To start the calibration the device must be in PLL_ON or RX_ON state. The
completion of the center frequency tuning is indicated by a PLL_LOCK interrupt.
Both calibration loops may be run simultaneously.
Two
IRQ_0 (PLL_LOCK) indicates that the PLL has locked. IRQ_1 (PLL_UNLOCK) interrupt
indicates an unexpected unlock condition. A PLL_LOCK interrupt clears any preceding
PLL_UNLOCK interrupt automatically and vice versa.
An IRQ_0 (PLL_LOCK) interrupt is supposed to occur in the following situations:
 State change from TRX_OFF to PLL_ON / RX_ON / TX_ARET_ON / RX_AACK_ON
 Channel change in states PLL_ON / RX_ON / TX_ARET_ON / RX_AACK_ON
Any other occurrences of PLL interrupts indicate erroneous behavior and require
checking of the actual device status.
The state transition from BUSY_TX to PLL_ON after successful transmission does not
generate an IRQ_0 (PLL_LOCK) within the settling period.
Register 0x08 (PHY_CC_CCA):
The PHY_CC_CCA register is a multi-purpose register that controls CCA configuration,
CCA measurement, and the IEEE 802.15.4 channel setting.
Figure 9-15. Register PHY_CC_CCA.
different
CCA_REQUEST
R/W
R/W
7
0
3
1
interrupts
indicate
R/W
R/W
6
0
2
0
CCA_MODE
CHANNEL
the
PLL
R/W
R/W
5
1
1
1
status
(refer
CHANNEL
R/W
R/W
4
0
0
1
AT86RF232
to
register 0x0F).
PHY_CC_CCA
PHY_CC_CCA
119