AT89C55WD Atmel Corporation, AT89C55WD Datasheet - Page 10
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AT89C55WD
Manufacturer Part Number
AT89C55WD
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT89C55WD.pdf
(35 pages)
Specifications of AT89C55WD
Flash (kbytes)
20 Kbytes
Max. Operating Frequency
24 MHz
Cpu
8051-12C
Max I/o Pins
32
Uart
1
Sram (kbytes)
0.25
Operating Voltage (vcc)
4.0 to 6.0
Timers
3
Watchdog
Yes
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8. Using the WDT
9. WDT During Power-down and Idle
10. UART
11. Timer 0 and 1
10
AT89C55WD
To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH
and 0E1H to WDTRST to avoid a WDT overflow. The 13-bit counter overflows when it reaches
8191 (1FFFH), and this will reset the device. When the WDT is enabled, it will increment every
machine cycle while the oscillator is running. This means the user must re-initialize the WDT at
least every 8191 machine cycles. To re-initialize the WDT the user must write 01EH and 0E1H
to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written.
When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse
duration is 98xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be
serviced in those sections of code that will periodically be executed within the time required to
prevent a WDT reset.
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-
down mode, the user does not need to service the WDT. There are two methods of exiting
Power-down mode: by a hardware reset or via a level-activated external interrupt which is
enabled prior to entering Power-down mode. When Power-down is exited with hardware reset,
servicing the WDT should occur as it normally does whenever the AT89C55WD is reset. Exiting
Power-down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent
the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until
the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for
the interrupt used to exit Power-down.
To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to
reset the WDT just before entering Power-down.
Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether
the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0)
as the default state. To prevent the WDT from resetting the AT89C55WD while in IDLE mode,
the user should always set up a timer that will periodically exit IDLE, service the WDT, and reen-
ter IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count
upon exit from IDLE.
The UART in the AT89C55WD operates the same way as the UART in the AT89C51 and
AT89C52. For more detailed information on the UART operation, please click on the document
link below:
Timer 0 and Timer 1 in the AT89C55WD operate the same way as Timer 0 and Timer 1 in the
AT89C51 and AT89C52. For further information on the timers’ operation, please click on the
document link below:
http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF
http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF
1921D–MICRO–6/08