AT89LP216 Atmel Corporation, AT89LP216 Datasheet - Page 18

• Manufacturer Part Number: AT89LP216
• Manufacturer: Atmel Corporation

Specifications of AT89LP216

• Flash (kbytes): 2 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 14
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.125
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 2
• Isp: SPI/OCD
• Watchdog: Yes

Table 11-1.
12. Interrupts
18
Symbol
SMOD1
SMOD0
PWDEX
POF
GF1, GF0
PD
IDL
PCON = 87H
Not Bit Addressable
Bit
AT89LP216
Function
Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3.
Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after
a frame error regardless of the state of SMOD0.
Power-down Exit Mode. When PWDEX = 1, wake up from Power-down is externally controlled. When PWDEX = 1, wake
up from Power-down is internally timed.
Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset under software control and is not
affected by RST or BOD (i.e. warm resets).
General-purpose Flags
Power-down bit. Setting this bit activates power-down operation.
Idle Mode bit. Setting this bit activates Idle mode operation
PCON
SMOD1
7
– Power Control Register
The AT89LP216 provides 7 interrupt sources: two external interrupts, two timer interrupts, a
serial port interrupt, a general-purpose interrupt, and an analog comparator interrupt. These
interrupts and the system reset each have a separate program vector at the start of the program
memory space. Each interrupt source can be individually enabled or disabled by setting or clear-
ing a bit in the interrupt enable register IE. The IE register also contains a global disable bit, EA,
which disables all interrupts.
Each interrupt source (except the analog comparator) can be individually programmed to one of
four priority levels by setting or clearing bits in the interrupt priority registers IP and IPH. The
analog comparator is fixed at the lowest priority level. An interrupt service routine in progress
can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower
priority. The highest priority interrupt cannot be interrupted by any other interrupt source. If two
requests of different priority levels are pending at the end of an instruction, the request of higher
priority level is serviced. If requests of the same priority level are pending at the end of an
instruction, an internal polling sequence determines which request is serviced. The polling
sequence is based on the vector address; an interrupt with a lower vector address has higher
priority than an interrupt with a higher vector address. Note that the polling sequence is only
used to resolve pending requests of the same priority level.
The External Interrupts INT0 and INT1 can each be either level-activated or edge-activated,
depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these inter-
rupts are the IE0 and IE1 bits in TCON. When the service routine is vectored to, hardware clears
the flag that generated an external interrupt only if the interrupt was edge-activated. If the inter-
rupt was level activated, then the external requesting source (rather than the on-chip hardware)
controls the request flag.
SMOD0
6
PWDEX
5
POF
4
GF1
3
GF0
2
Reset Value = 000X 0000B
PD
1
3621E–MICRO–11/10
IDL
0