AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 100

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

17.1
100
Master Operation
AT89LP3240/6440
Figure 17-2. SPI Master-Slave Interconnection
When the SPI is configured as a Master (MSTR in SPCR is set), the operation of the SS pin
depends on the setting of the Slave Select Ignore bit, SSIG. If SSIG = 1, the SS pin is a general
purpose output pin which does not affect the SPI system. Typically, the pin will be driving the SS
pin of an SPI Slave. If SSIG = 0, SS must be held high to ensure Master SPI operation. If the SS
pin is driven low by peripheral circuitry when the SPI is configured as a Master with SSIG = 0,
the SPI system interprets this as another master selecting the SPI as a slave and starting to
send data to it. To avoid bus contention, the SPI system takes the following actions:
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi-
bility that SS may be driven low, the interrupt should always check that the MSTR bit is still set. If
the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI
Master mode.
An SPI master device initiates all data transfers on the SPI bus. The AT89LP3240/6440 is con-
figured for master operation by setting MSTR = 1 in SPCR. Writing to the SPI data register
(SPDR) while in master mode loads the transmit buffer. If the SPI shift register is empty, the byte
in the transmit buffer is moved to the shift register; the transmit buffer empty flag, TXE, is set;
and a transmission begins. The transfer may start after an initial delay, while the clock generator
waits for the next full bit slot of the specified baud rate. The master shifts the data out serially on
the MOSI line while providing the serial shift clock on SCK. When the transfer finishes, the SPIF
flag is set to “1” and an interrupt request is generated, if enabled. The data received from the
addressed SPI slave device is also transferred from the shift register to the receive buffer.
Therefore, the SPIF bit flags both the transmit-complete and receive-data-ready conditions. The
received data is accessed by reading SPDR.
While the TXE flag is set, the transmit buffer is empty. TXE can be cleared by software or by
writing to SPDR. Writing to SPDR will clear TXE and load the transmit buffer. The user may load
the buffer while the shift register is busy, i.e. before the current transfer completes. When the
current transfer completes, the queued byte in the transmit buffer is moved to the shift register
and the next transfer commences. TXE will generate an interrupt if the SPI interrupt is enabled
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of
2. The MODF Flag in SPSR is set, and if the SPI interrupt is enabled, the interrupt routine
the SPI becoming a Slave, the MOSI and SCK pins become inputs.
will be executed.
MSB
Generator
Clock
8-Bit Shift Register
Master
MODF
LSB
GPIO
SSIG
SS
MISO
MOSI
SCK
V
CC
MISO
MOSI
SCK
SS
SSIG
MSB
DISSO
8-Bit Shift Register
Slave
3706C–MICRO–2/11
LSB